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ISP1181B
Full-speed Universal Serial Bus interface device
Rev. 01 -- 03 July 2002 Product data
1. General description
The ISP1181B is a Universal Serial Bus (USB) interface device which complies with Universal Serial Bus Specification Rev. 2.0 (full speed). It provides full-speed USB communication capacity to microcontroller or microprocessor-based systems. The ISP1181B communicates with the system's microcontroller or microprocessor through a high-speed general-purpose parallel interface. The ISP1181B supports fully autonomous, multi-configurable Direct Memory Access (DMA) operation. The modular approach to implementing a USB interface device allows the designer to select the optimum system microcontroller from the wide variety available. The ability to re-use existing architecture and firmware investments shortens development time, eliminates risks and reduces costs. The result is fast and efficient development of the most cost-effective USB peripheral solution. The ISP1181B is ideally suited for application in many personal computer peripherals, such as printers, communication devices, scanners, external mass storage (Zip(R) drive) devices and digital still cameras. It offers an immediate cost reduction for applications that currently use SCSI implementations.
2. Features
s Complies with Universal Serial Bus Specification Rev. 2.0 (full speed) and most Device Class specifications s High performance USB interface device with integrated Serial Interface Engine (SIE), FIFO memory, transceiver and 3.3 V voltage regulator s High speed (11.1 Mbyte/s or 90 ns read/write cycle) parallel interface s Fully autonomous and multi-configuration DMA operation s Up to 14 programmable USB endpoints with 2 fixed control IN/OUT endpoints s Integrated physical 2462 bytes of multi-configuration FIFO memory s Endpoints with double buffering to increase throughput and ease real-time data transfer s Seamless interface with most microcontrollers/microprocessors s Bus-powered capability with low power consumption and low `suspend' current s 6 MHz crystal oscillator input with integrated PLL for low EMI s Controllable LazyClock (100 50% kHz) output during `suspend' s Software controlled connection to the USB bus (SoftConnectTM) s Good USB connection indicator that blinks with traffic (GoodLinkTM) s Clock output with programmable frequency (up to 48 MHz)
Philips Semiconductors
ISP1181B
Full-speed USB interface
s Complies with the ACPITM, OnNowTM and USB power management requirements s Internal power-on and low-voltage reset circuit, with possibility of a software reset s Operation over the extended USB bus voltage range (4.0 to 5.5 V) with 5 V tolerant I/O pads s Operating temperature range -40 to +85 C s Full-scan design with high fault coverage s Available in TSSOP48 and HVQFN48 packages.
3. Applications
s Personal Digital Assistant (PDA) s Digital camera s Communication device, e.g., x Router x Modem s Mass storage device, e.g., x Zip(R) drive s Printer s Scanner.
4. Ordering information
Table 1: Ordering information Package Name ISP1181BDGG ISP1181BBS TSSOP48 HVQFN48 Description Plastic thin shrink small outline package; 48 leads; body width 6.1 mm Plastic thermal enhanced very thin quad flat package; no leads; 48 terminals; body 7 x 7 x 0.85 mm Version SOT362-1 SOT619-2 Type number
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Product data
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Product data Rev. 01 -- 03 July 2002
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5. Block diagram
Philips Semiconductors
to/from USB D+ D- VBUS sense input 5 3.3 V 1.5 k SoftConnect 4 6 GL to LED 7 HUB GoodLink
6 MHz CLKOUT XTAL1 48 XTAL2 47 48 MHz PROGR. DIVIDER DMA HANDLER 45 11 DREQ EOT, DACK 2 10, 12 17 18 to/from microcontroller BUS_CONF0 BUS_CONF1
PLL OSCILLATOR BIT CLOCK RECOVERY
ANALOG Tx/Rx
PHILIPS SIE
MEMORY MANAGEMENT UNIT
MICRO CONTROLLER HANDLER
38, 35 to 27, 24 to 19 16 BUS INTERFACE 43 to 39 5
AD0, DATA1 to DATA9, DATA10 to DATA15 CS, ALE, WR, RD, A0
RESET
44 POWER-ON RESET internal reset INTEGRATED RAM ENDPOINT HANDLER 15 INT
VCC
1
VOLTAGE REGULATOR
3.3 V
3.3 V
INTERNAL SUPPLY
I/O PIN SUPPLY
ISP1181B
2
3
9
8
25, 36, 46 3
37
26
004aaa134
Full-speed USB interface
REGGND
Vreg(3.3)
SUSPEND WAKEUP
GND
VCC(3.3)
Vref
ISP1181B
Fig 1. Block diagram.
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ISP1181B
Full-speed USB interface
6. Pinning information
6.1 Pinning
VCC 1 REGGND 2 Vreg(3.3) 3 D- 4 D+ 5 VBUS 6 GL 7 WAKEUP 8 SUSPEND 9 EOT 10 DREQ 11 DACK 12
48 XTAL1 47 XTAL2 46 GND 45 CLKOUT 44 RESET 43 CS 42 ALE 41 WR 40 RD 39 A0 38 AD0 37 VCC(3.3)
ISP1181BDGG
TEST1 13 TEST2 14 INT 15 TEST3 16 BUS_CONF0 17 BUS_CONF1 18 DATA15 19 DATA14 20 DATA13 21 DATA12 22 DATA11 23 DATA10 24
004aaa135
36 GND 35 DATA1 34 DATA2 33 DATA3 32 DATA4 31 DATA5 30 DATA6 29 DATA7 28 DATA8 27 DATA9 26 Vref 25 GND
Fig 2. Pin configuration TSSOP48.
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ISP1181B
Full-speed USB interface
13 BUS_CONF1 14 DATA15
15 DATA14 16 DATA13 17 DATA12
18 DATA11 19 DATA10
BUS_CONF0 12 TEST3 11 TEST2 TEST1 DACK DREQ EOT SUSPEND WAKEUP GL VBUS INT 10 9 8 7 6 5 4 3 2 1 Vreg(3.3) 46 REGGND 45 VCC 44 XTAL1 43 XTAL2 42 GND 41 CLKOUT 40 RESET 39 CS 38 ALE 37 D+ 48 D- 47
23 DATA8 24 DATA7 25 DATA6 26 DATA5 27 DATA4 28 DATA3 29 DATA2 30 DATA1 31 GND 32 VCC(3.3) 33 AD0 34 A0 35 RD 36 WR
ISP1181BBS
Bottom view
22 DATA9
20 GND 21 Vref
004aaa136
Fig 3. Pin configuration HVQFN48.
6.2 Pin description
Table 2: Symbol[1] VCC REGGND Vreg(3.3) Pin description Pin TSSOP48 1 2 3 HVQFN48 44 45 46 supply voltage (3.3 or 5.0 V) voltage regulator ground supply regulated supply voltage (3.3 V 10%) from internal regulator; used to connect decoupling capacitor and pull-up resistor on D+ line; Remark: Cannot be used to supply external devices. D- D+ VBUS GL 4 5 6 7 47 48 1 2 AI/O AI/O I O USB D- connection (analog) USB D+ connection (analog) VBUS sensing input GoodLink LED indicator output (open-drain, 8 mA); the LED is default ON, blinks OFF upon USB traffic; to connect an LED use a series resistor of 470 (VCC = 5.0 V) or 330 (VCC = 3.3 V) wake-up input (edge triggered, LOW to HIGH); generates a remote wake-up from `suspend' state `suspend' state indicator output (4 mA); used as power switch control output (active LOW) for powered-off application
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Type
Description
WAKEUP
8
3
I
SUSPEND
9
4
O
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ISP1181B
Full-speed USB interface
Pin description...continued Pin TSSOP48 HVQFN48 5 I End-Of-Transfer input (programmable polarity, see Table 22); used by the DMA controller to force the end of a DMA transfer to the ISP1181B DMA request output (4 mA; programmable polarity, see Table 22); signals to the DMA controller that the ISP1181B wants to start a DMA transfer DMA acknowledge input (programmable polarity, see Table 22); used by the DMA controller to signal the start of a DMA transfer requested by the ISP1181B test input; this pin must be connected to VCC via an external 10 k resistor test input; this pin must be connected to VCC via an external 10 k resistor interrupt output; programmable polarity (active HIGH or LOW) and signalling (level or pulse); see Table 22 test output; this pin is used for test purposes only bus configuration selector; see Table 3 bus configuration selector; see Table 3 bit 15 of D[15:0]; bi-directional data line (slew-rate controlled output, 4 mA) bit 14 of D[15:0]; bi-directional data line (slew-rate controlled output, 4 mA) bit 13 of D[15:0]; bi-directional data line (slew-rate controlled output, 4 mA) bit 12 of D[15:0]; bi-directional data line (slew-rate controlled output, 4 mA) bit 11 of D[15:0]; bi-directional data line (slew-rate controlled output, 4 mA) bit 10 of D[15:0]; bi-directional data line (slew-rate controlled output, 4 mA) ground supply I/O pin reference voltage (3.3 V); no connection if VCC = 5.0 V bit 9 of D[15:0]; bi-directional data line (slew-rate controlled output, 4 mA) bit 8 of D[15:0]; bi-directional data line (slew-rate controlled output, 4 mA) bit 7 of D[15:0]; bi-directional data line (slew-rate controlled output, 4 mA) bit 6 of D[15:0]; bi-directional data line (slew-rate controlled output, 4 mA)
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Table 2: Symbol[1] EOT
Type
Description
10
DREQ
11
6
O
DACK
12
7
I
TEST1 TEST2 INT
13 14 15
8 9 10
I I O
TEST3 BUS_CONF0 BUS_CONF1 DATA15 DATA14 DATA13 DATA12 DATA11 DATA10 GND Vref DATA9 DATA8 DATA7 DATA6
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
O I I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
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ISP1181B
Full-speed USB interface
Pin description...continued Pin TSSOP48 HVQFN48 26 27 28 29 30 31 32 33 I/O I/O I/O I/O I/O I/O bit 5 of D[15:0]; bi-directional data line (slew-rate controlled output, 4 mA) bit 4 of D[15:0]; bi-directional data line (slew-rate controlled output, 4 mA) bit 3 of D[15:0]; bi-directional data line (slew-rate controlled output, 4 mA) bit 2 of D[15:0]; bi-directional data line (slew-rate controlled output, 4 mA) bit 1 of D[15:0]; bi-directional data line (slew-rate controlled output, 4 mA) ground supply supply voltage (3.0 to 3.6 V); leave this pin unconnected when using VCC = 5.0 V multiplexed bi-directional address and data line; represents address A0 or bit 0 of D[15:0] in conjunction with input ALE; level-sensitive input or slew-rate controlled output (4 mA) Address phase: a HIGH-to-LOW transition on input ALE latches the level on this pin as address A0 (1 = command, 0 = data) Data phase: during reading this pin outputs bit D[0]; during writing the level on this pin is latched as bit D[0] 31 32 33 34 35 36 37 38 Type Description
Table 2: Symbol[1] DATA5 DATA4 DATA3 DATA2 DATA1 GND VCC(3.3) AD0
A0
39
34
I
address input; selects command (A0 = 1) or data (A0 = 0); in a multiplexed address/data bus configuration this pin is not used and must be tied LOW (connect to GND) read strobe input write strobe input address latch enable input; a HIGH-to-LOW transition latches the level on pin AD0 as address information in a multiplexed address/data bus configuration; must be tied LOW (connect to GND) for a separate address/data bus configuration chip select input reset input (Schmitt trigger); a LOW level produces an asynchronous reset; connect to VCC for power-on reset (internal POR circuit) programmable clock output (2 mA)
RD WR ALE
40 41 42
35 36 37
I I I
CS RESET
43 44
38 39
I I
CLKOUT
45
40
O
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ISP1181B
Full-speed USB interface
Pin description...continued Pin TSSOP48 HVQFN48 41 42 O ground supply crystal oscillator output (6 MHz); connect a fundamental parallel-resonant crystal; leave this pin open when using an external clock source on pin XTAL1 crystal oscillator input (6 MHz); connect a fundamental parallel-resonant crystal or an external clock source (leave pin XTAL2 unconnected) 46 47 Type Description
Table 2: Symbol[1] GND XTAL2
XTAL1
48
43
I
[1]
Symbol names with an overscore (e.g. NAME) represent active LOW signals.
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ISP1181B
Full-speed USB interface
7. Functional description
The ISP1181B is a full-speed USB interface device with up to 14 configurable endpoints. It has a fast general-purpose parallel interface for communication with many types of microcontrollers or microprocessors. It supports different bus configurations (see Table 3) and local DMA transfers of up to 16 bytes per cycle. The block diagram is given in Figure 1. The ISP1181B has 2462 bytes of internal FIFO memory, which is shared among the enabled USB endpoints. The type and FIFO size of each endpoint can be individually configured, depending on the required packet size. Isochronous and bulk endpoints are double-buffered for increased data throughput. The ISP1181B requires a single supply voltage of 3.3 or 5.0 V and has an internal 3.3 V voltage regulator for powering the analog USB transceiver. It supports bus-powered operation. The ISP1181B operates on a 6 MHz oscillator frequency. A programmable clock output is available up to 48 MHz. During `suspend' state the 100 50% kHz LazyClock frequency can be output.
7.1 Analog transceiver
The transceiver is compliant with the Universal Serial Bus Specification Rev. 2.0 (full speed). It interfaces directly with the USB cable through external termination resistors.
7.2 Philips Serial Interface Engine (SIE)
The Philips SIE implements the full USB protocol layer. It is completely hardwired for speed and needs no firmware intervention. The functions of this block include: synchronization pattern recognition, parallel/serial conversion, bit (de-)stuffing, CRC checking/generation, Packet IDentifier (PID) verification/generation, address recognition, handshake evaluation/generation.
7.3 Memory Management Unit (MMU) and integrated RAM
The MMU and the integrated RAM provide the conversion between the USB speed (12 Mbit/s bursts) and the parallel interface to the microcontroller (max. 12 Mbyte/s). This allows the microcontroller to read and write USB packets at its own speed.
7.4 SoftConnect
The connection to the USB is accomplished by bringing D+ (for full-speed USB devices) HIGH through a 1.5 k pull-up resistor. In the ISP1181B the 1.5 k pull-up resistor is integrated on-chip and is not connected to VCC by default. The connection is established by a command sent from the external/system microcontroller. This allows the system microcontroller to complete its initialization sequence before deciding to establish connection with the USB. Re-initialization of the USB connection can also be performed without disconnecting the cable. The ISP1181B will check for USB VBUS availability before the connection can be established. VBUS sensing is provided through pin VBUS.
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ISP1181B
Full-speed USB interface
VBUS sensing prevents the device from wake-up when VBUS is not present. Without VBUS sensing, any activity or noise on (D+, D-) might wake up the device. With VBUS sensing, (D+, D-) is decoupled when no VBUS is present. Therefore, even if there is noise on the (D+, D-) lines, it is not taken into account. This ensures that the device remains in the `suspend' state. Remark: Note that the tolerance of the internal resistors is 25%. This is higher than the 5 % tolerance specified by the USB specification. However, the overall VSE voltage specification for the connection can still be met with a good margin. The decision to make use of this feature lies with the USB equipment designer.
7.5 GoodLink
Indication of a good USB connection is provided at pin GL through GoodLink technology. During enumeration the LED indicator will blink on momentarily. When the ISP1181B has been successfully enumerated (the device address is set), the LED indicator will remain permanently on. Upon each successful packet transfer (with ACK) to and from the ISP1181B the LED will blink off for 100 ms. During `suspend' state the LED will remain off. This feature provides a user-friendly indication of the status of the USB device, the connected hub and the USB traffic. It is a useful field diagnostics tool for isolating faulty equipment. It can therefore help to reduce field support and hotline overhead.
7.6 Bit clock recovery
The bit clock recovery circuit recovers the clock from the incoming USB data stream using a 4x over-sampling principle. It is able to track jitter and frequency drift as specified by the USB Specification Rev. 2.0.
7.7 Voltage regulator
A 5 V to 3.3 V voltage regulator is integrated on-chip to supply the analog transceiver and internal logic. This voltage is available at pin Vreg(3.3) to supply an external 1.5 k pull-up resistor on the D+ line. Alternatively, the ISP1181B provides SoftConnect technology via an integrated 1.5 k pull-up resistor (see Section 7.4).
7.8 PLL clock multiplier
A 6 MHz to 48 MHz clock multiplier Phase-Locked Loop (PLL) is integrated on-chip. This allows for the use of a low-cost 6 MHz crystal, which also minimizes EMI. No external components are required for the operation of the PLL.
7.9 Parallel I/O (PIO) and Direct Memory Access (DMA) interface
A generic PIO interface is defined for speed and ease-of-use. It also allows direct interfacing to most microcontrollers. To a microcontroller, the ISP1181B appears as a memory device with an 8/16-bit data bus and an 1-bit address bus. The ISP1181B supports both multiplexed and non-multiplexed address and data buses. The ISP1181B can also be configured as a DMA slave device to allow more efficient data transfer. One of the 14 endpoint FIFOs may directly transfer data to/from the local shared memory. The DMA interface can be configured independently from the PIO interface.
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ISP1181B
Full-speed USB interface
8. Modes of operation
The ISP1181B has four bus configuration modes, selected via pins BUS_CONF1 and BUS_CONF0: Mode 0 Mode 1 Mode 2 Mode 3 16-bit I/O port shared with 16-bit DMA port reserved 8-bit I/O port shared with 8-bit DMA port reserved.
The bus configurations for each of these modes are given in Table 3. Typical interface circuits for each mode are given in Section 21.1.
Table 3: Mode 0 Bus configuration modes BUS_CONF[1:0] 0 0 PIO width D[15:1], AD0 DMA width DMAWD = 0 DMAWD = 1 D[15:1], AD0 multiplexed address/data on pin AD0; bus is shared by 16-bit I/O port and 16-bit DMA port reserved multiplexed address/data on pin AD0; bus is shared by 8-bit I/O port and 8-bit DMA port reserved Description
1 2
0 1
1 0
reserved D[7:1], AD0
reserved D[7:1], AD0
reserved -
3
1
1
reserved
reserved
reserved
9. Endpoint descriptions
Each USB device is logically composed of several independent endpoints. An endpoint acts as a terminus of a communication flow between the host and the device. At design time each endpoint is assigned a unique number (endpoint identifier, see Table 4). The combination of the device address (given by the host during enumeration), the endpoint number and the transfer direction allows each endpoint to be uniquely referenced. The ISP1181B has 16 endpoints: endpoint 0 (control IN and OUT) plus 14 configurable endpoints, which can be individually defined as interrupt/bulk/isochronous, IN or OUT. Each enabled endpoint has an associated FIFO, which can be accessed either via the parallel I/O interface or via DMA.
9.1 Endpoint access
Table 4 lists the endpoint access modes and programmability. All endpoints support I/O mode access. Endpoints 1 to 14 also support DMA access. FIFO DMA access is selected and enabled via bits EPIDX[3:0] and DMAEN of the DMA Configuration Register. A detailed description of the DMA operation is given in Section 10.
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ISP1181B
Full-speed USB interface
Table 4: Endpoint identifier 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
[1] [2]
Endpoint access and programmability FIFO size (bytes)[1] 64 (fixed) 64 (fixed) programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable Double buffering no no supported supported supported supported supported supported supported supported supported supported supported supported supported supported I/O mode access yes yes supported supported supported supported supported supported supported supported supported supported supported supported supported supported DMA mode access no no supported supported supported supported supported supported supported supported supported supported supported supported supported supported Endpoint type control OUT[2] control IN[2] programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable
The total amount of FIFO storage allocated to enabled endpoints must not exceed 2462 bytes. IN: input for the USB host (ISP1181B transmits); OUT: output from the USB host (ISP1181B receives). The data flow direction is determined by bit EPDIR in the Endpoint Configuration Register.
9.2 Endpoint FIFO size
The size of the FIFO determines the maximum packet size that the hardware can support for a given endpoint. Only enabled endpoints are allocated space in the shared FIFO storage, disabled endpoints have zero bytes. Table 5 lists the programmable FIFO sizes. The following bits in the Endpoint Configuration Register (ECR) affect FIFO allocation:
* Endpoint enable bit (FIFOEN) * Size bits of an enabled endpoint (FFOSZ[3:0]) * Isochronous bit of an enabled endpoint (FFOISO).
Remark: Register changes that affect the allocation of the shared FIFO storage among endpoints must not be made while valid data is present in any FIFO of the enabled endpoints. Such changes will render all FIFO contents undefined.
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ISP1181B
Full-speed USB interface
Programmable FIFO size Non-isochronous 8 bytes 16 bytes 32 bytes 64 bytes reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved Isochronous 16 bytes 32 bytes 48 bytes 64 bytes 96 bytes 128 bytes 160 bytes 192 bytes 256 bytes 320 bytes 384 bytes 512 bytes 640 bytes 768 bytes 896 bytes 1023 bytes
Table 5: 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
FFOSZ[3:0]
Each programmable FIFO can be configured independently via its ECR, but the total physical size of all enabled endpoints (IN plus OUT) must not exceed 2462 bytes (512 bytes for non-isochronous FIFOs). Table 6 shows an example of a configuration fitting in the maximum available space of 2462 bytes. The total number of logical bytes in the example is 1311. The physical storage capacity used for double buffering is managed by the device hardware and is transparent to the user.
Table 6: Memory configuration example Logical size (bytes) 64 64 1023 16 16 64 64 Endpoint description control IN (64 byte fixed) control OUT (64 byte fixed) double-buffered 1023-byte isochronous endpoint 16-byte interrupt OUT 16-byte interrupt IN double-buffered 64-byte bulk OUT double-buffered 64-byte bulk IN
Physical size (bytes) 64 64 2046 16 16 128 128
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ISP1181B
Full-speed USB interface
9.3 Endpoint initialization
In response to the standard USB request Set Interface, the firmware must program all 16 ECRs of the ISP1181B in sequence (see Table 4), whether the endpoints are enabled or not. The hardware will then automatically allocate FIFO storage space. If all endpoints have been configured successfully, the firmware must return an empty packet to the control IN endpoint to acknowledge success to the host. If there are errors in the endpoint configuration, the firmware must stall the control IN endpoint. When reset by hardware or via the USB bus, the ISP1181B disables all endpoints and clears all ECRs, except for the control endpoint which is fixed and always enabled. Endpoint initialization can be done at any time; however, it is valid only after enumeration.
9.4 Endpoint I/O mode access
When an endpoint event occurs (a packet is transmitted or received), the associated endpoint interrupt bits (EPn) of the Interrupt Register (IR) will be set by the SIE. The firmware then responds to the interrupt and selects the endpoint for processing. The endpoint interrupt bit will be cleared by reading the Endpoint Status Register (ESR). The ESR also contains information on the status of the endpoint buffer. For an OUT (= receive) endpoint, the packet length and packet data can be read from ISP1181B using the Read Buffer command. When the whole packet has been read, the firmware sends a Clear Buffer command to enable the reception of new packets. For an IN (= transmit) endpoint, the packet length and data to be sent can be written to ISP1181B using the Write Buffer command. When the whole packet has been written to the buffer, the firmware sends a Validate Buffer command to enable data transmission to the host.
9.5 Special actions on control endpoints
Control endpoints require special firmware actions. The arrival of a SETUP packet flushes the IN buffer and disables the Validate Buffer and Clear Buffer commands for the control IN and OUT endpoints. The microcontroller needs to re-enable these commands by sending an Acknowledge Setup command to both control endpoints. This ensures that the last SETUP packet stays in the buffer and that no packets can be sent back to the host until the microcontroller has explicitly acknowledged that it has seen the SETUP packet.
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ISP1181B
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10. DMA transfer
Direct Memory Access (DMA) is a method to transfer data from one location to another in a computer system, without intervention of the central processor (CPU). Many different implementations of DMA exist. The ISP1181B supports two methods:
* 8237 compatible mode: based on the DMA subsystem of the IBM personal
computers (PC, AT and all its successors and clones); this architecture uses the Intel 8237 DMA controller and has separate address spaces for memory and I/O
* DACK-only mode: based on the DMA implementation in some embedded RISC
processors, which has a single address space for both memory and I/O. The ISP1181B supports DMA transfer for all 14 configurable endpoints (see Table 4). Only one endpoint at a time can be selected for DMA transfer. The DMA operation of the ISP1181B can be interleaved with normal I/O mode access to other endpoints. The following features are supported:
* Single-cycle or burst transfers (up to 16 bytes per cycle) * Programmable transfer direction (read or write) * Multiple End-Of-Transfer (EOT) sources: external pin, internal conditions,
short/empty packet
* Programmable signal levels on pins DREQ, DACK and EOT. 10.1 Selecting an endpoint for DMA transfer
The target endpoint for DMA access is selected via bits EPDIX[3:0] in the DMA Configuration Register, as shown in Table 7. The transfer direction (read or write) is automatically set by bit EPDIR in the associated ECR, to match the selected endpoint type (OUT endpoint: read; IN endpoint: write). Asserting input DACK automatically selects the endpoint specified in the DMA Configuration Register, regardless of the current endpoint used for I/O mode access.
Table 7: Endpoint selection for DMA transfer EPIDX[3:0] 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 Transfer direction EPDIR = 0 OUT: read OUT: read OUT: read OUT: read OUT: read OUT: read OUT: read OUT: read OUT: read OUT: read OUT: read EPDIR = 1 IN: write IN: write IN: write IN: write IN: write IN: write IN: write IN: write IN: write IN: write IN: write
Endpoint identifier 1 2 3 4 5 6 7 8 9 10 11
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Endpoint selection for DMA transfer...continued EPIDX[3:0] 1101 1110 1111 Transfer direction EPDIR = 0 OUT: read OUT: read OUT: read EPDIR = 1 IN: write IN: write IN: write
Table 7:
Endpoint identifier 12 13 14
10.2 8237 compatible mode
The 8237 compatible DMA mode is selected by clearing bit DAKOLY in the Hardware Configuration Register (see Table 21). The pin functions for this mode are shown in Table 8.
Table 8: Symbol DREQ DACK EOT RD WR 8237 compatible mode: pin functions Description DMA request DMA acknowledge end of transfer read strobe write strobe I/O O I I I I Function ISP1181B requests a DMA transfer DMA controller confirms the transfer DMA controller terminates the transfer instructs ISP1181B to put data on the bus instructs ISP1181B to get data from the bus
The DMA subsystem of an IBM compatible PC is based on the Intel 8237 DMA controller. It operates as a `fly-by' DMA controller: the data is not stored in the DMA controller, but it is transferred between an I/O port and a memory address. A typical example of ISP1181B in 8237 compatible DMA mode is given in Figure 4. The 8237 has two control signals for each DMA channel: DREQ (DMA Request) and DACK (DMA Acknowledge). General control signals are HRQ (Hold Request), HLDA (Hold Acknowledge) and EOP (End-Of-Process). The bus operation is controlled via MEMR (Memory Read), MEMW (Memory Write), IOR (I/O read) and IOW (I/O write).
AD0, DATA1 to DATA15
RAM
MEMR MEMW
ISP1181B
DREQ DACK RD WR
DMA CONTROLLER 8237
DREQ DACK IOR IOW HRQ HLDA
CPU
HRQ HLDA
004aaa137
Fig 4. ISP1181B in 8237 compatible DMA mode.
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The following example shows the steps which occur in a typical DMA transfer: 1. ISP1181B receives a data packet in one of its endpoint FIFOs; the packet must be transferred to memory address 1234H. 2. ISP1181B asserts the DREQ signal requesting the 8237 for a DMA transfer. 3. The 8237 asks the CPU to release the bus by asserting the HRQ signal. 4. After completing the current instruction cycle, the CPU places the bus control signals (MEMR, MEMW, IOR and IOW) and the address lines in three-state and asserts HLDA to inform the 8237 that it has control of the bus. 5. The 8237 now sets its address lines to 1234H and activates the MEMW and IOR control signals. 6. The 8237 asserts DACK to inform the ISP1181B that it will start a DMA transfer. 7. The ISP1181B now places the byte or word to be transferred on the data bus lines, because its RD signal was asserted by the 8237. 8. The 8237 waits one DMA clock period and then de-asserts MEMW and IOR. This latches and stores the byte or word at the desired memory location. It also informs the ISP1181B that the data on the bus lines has been transferred. 9. The ISP1181B de-asserts the DREQ signal to indicate to the 8237 that DMA is no longer needed. In Single cycle mode this is done after each byte or word, in Burst mode following the last transferred byte or word of the DMA cycle. 10. The 8237 de-asserts the DACK output indicating that the ISP1181B must stop placing data on the bus. 11. The 8237 places the bus control signals (MEMR, MEMW, IOR and IOW) and the address lines in three-state and de-asserts the HRQ signal, informing the CPU that it has released the bus. 12. The CPU acknowledges control of the bus by de-asserting HLDA. After activating the bus control lines (MEMR, MEMW, IOR and IOW) and the address lines, the CPU resumes the execution of instructions. For a typical bulk transfer the above process is repeated 64 times, once for each byte. After each byte the address register in the DMA controller is incremented and the byte counter is decremented. When using 16-bit DMA the number of transfers is 32 and address incrementing and byte counter decrementing is done by 2 for each word.
10.3 DACK-only mode
The DACK-only DMA mode is selected by setting bit DAKOLY in the Hardware Configuration Register (see Table 21). The pin functions for this mode are shown in Table 9. A typical example of ISP1181B in DACK-only DMA mode is given in Figure 5.
Table 9: Symbol DREQ DACK EOT RD WR
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DACK-only mode: pin functions Description DMA request DMA acknowledge End-Of-Transfer read strobe write strobe I/O O I I I I Function ISP1181B requests a DMA transfer DMA controller confirms the transfer; also functions as data strobe DMA controller terminates the transfer not used not used
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In DACK-only mode the ISP1181B uses the DACK signal as data strobe. Input signals RD and WR are ignored. This mode is used in CPU systems that have a single address space for memory and I/O access. Such systems have no separate MEMW and MEMR signals: the RD and WR signals are also used as memory data strobes.
ISP1181B
DMA CONTROLLER
DREQ DACK HRQ HLDA RD WR
CPU
DREQ DACK
HRQ HLDA
AD0, DATA1 to DATA15
RAM
004aaa138
Fig 5. ISP1181B in DACK-only DMA mode.
10.4 End-Of-Transfer conditions
10.4.1 Bulk endpoints A DMA transfer to/from a bulk endpoint can be terminated by any of the following conditions (bit names refer to the DMA Configuration Register, see Table 25):
* An external End-Of-Transfer signal occurs on input EOT * The DMA transfer completes as programmed in the DMA Counter register
(CNTREN = 1)
* A short packet is received on an enabled OUT endpoint (SHORTP = 1) * DMA operation is disabled by clearing bit DMAEN.
External EOT: When reading from an OUT endpoint, an external EOT will stop the DMA operation and clear any remaining data in the current FIFO. For a doublebuffered endpoint the other (inactive) buffer is not affected. When writing to an IN endpoint, an EOT will stop the DMA operation and the data packet in the FIFO (even if it is smaller than the maximum packet size) will be sent to the USB host at the next IN token. DMA Counter Register: An EOT from the DMA Counter Register is enabled by setting bit CNTREN in the DMA Configuration Register. The ISP1181B has a 16-bit DMA Counter Register, which specifies the number of bytes to be transferred. When DMA is enabled (DMAEN = 1), the internal DMA counter is loaded with the value from the DMA Counter Register. When the internal counter completes the transfer as programmed in the DMA counter, an EOT condition is generated and the DMA operation stops.
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Short packet: Normally, the transfer byte count must be set via a control endpoint before any DMA transfer takes place. When a short packet has been enabled as EOT indicator (SHORTP = 1), the transfer size is determined by the presence of a short packet in the data. This mechanism permits the use of a fully autonomous data transfer protocol. When reading from an OUT endpoint, reception of a short packet at an OUT token will stop the DMA operation after transferring the data bytes of this packet.
Table 10: EOT input DMA Counter Register Summary of EOT conditions for a bulk endpoint OUT endpoint EOT is active transfer completes as programmed in the DMA Counter register short packet is received and transferred DMAEN = 0[1] IN endpoint EOT is active transfer completes as programmed in the DMA Counter register counter reaches zero in the middle of the buffer DMAEN = 0[1]
EOT condition
Short packet DMAEN bit in DMA Configuration Register
[1]
The DMA transfer stops. However, no interrupt is generated.
10.4.2
Isochronous endpoints A DMA transfer to/from an isochronous endpoint can be terminated by any of the following conditions (bit names refer to the DMA Configuration Register, see Table 25):
* An external End-Of-Transfer signal occurs on input EOT * The DMA transfer completes as programmed in the DMA Counter register
(CNTREN = 1)
* An End-Of-Packet (EOP) signal is detected * DMA operation is disabled by clearing bit DMAEN.
Table 11: Recommended EOT usage for isochronous endpoints OUT endpoint do not use do not use preferred IN endpoint preferred preferred do not use EOT condition EOT input active DMA Counter Register zero End-Of-Packet
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11. Suspend and resume
11.1 Suspend conditions
The ISP1181B detects a USB `suspend' status in the following cases:
* A J-state is present on the USB bus for 3 ms * VBUS is lost.
With SoftConnect disabled, ISP1181B does not go into the suspend state as long as VBUS is present. ISP1181B will remain in `suspend' state for at least 5 ms, before responding to external wake-up events such as global resume, bus traffic, wake-up on CS or WAKEUP. The typical timing is shown in Figure 6.
GOSUSP suspend >5 ms WAKEUP
MGS949
start detection of wake-up conditions
Fig 6. Typical suspend timing.
Bus-powered devices that are suspended must not consume more than 500 A of current. This is achieved by shutting down the power to system components or supplying them with a reduced voltage. ISP1181B is always in powered-off mode during `suspend' state. Default, bit PWROFF in the Hardware Configuration register is logic 1 and this value should not be changed under any condition. This powered-off mode is explained in detail in Section 11.1.1. The steps leading up to `suspend' status are as follows: 1. Upon detection of a `wake-up' to `suspend' transition ISP1181B sets bit SUSPND in the Interrupt Register. This will generate an interrupt if bit IESUSP in the Interrupt Enable Register is set. 2. When the firmware detects a `suspend' condition it must prepare all system components for `suspend' state: a. All signals connected to ISP1181B must enter appropriate states to meet the power consumption requirements of `suspend' state. b. All input pins of ISP1181B must have a CMOS logic 0 or logic 1 level. 3. In the interrupt service routine the firmware must check the current status of the USB bus. When bit BUSTATUS in the Interrupt Register is logic 0, the USB bus has left `suspend' mode and the process must be aborted. Otherwise, the next step can be executed.
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4. To meet the `suspend' current requirements for a bus-powered device, the internal clocks must be switched off by clearing bit CLKRUN in the Hardware Configuration Register. 5. When the firmware has set and cleared the GOSUSP bit in the Mode Register, the ISP1181B enters `suspend' state. In powered-off application, the ISP1181B asserts output SUSPEND and switches off the internal clocks after 2 ms. 11.1.1 Powered-off application In powered-off application (PWROFF = 1 in the Hardware Configuration Register) the supply of the CPU and other parts of the circuit is removed during `suspend' state. The SUSPEND output is active HIGH during `suspend' state, making it suitable as a power switch control signal, e.g. for an external oscillator. Input pins of ISP1181B are pulled to ground via the pin buffers. Outputs are made three-state to prevent current flowing in the application. Bi-directional pins are made three-state and must be pulled to ground externally by the application. The power supply of external pull-ups must also be removed to reduce power consumption.
GOSUSP
WAKEUP
2 ms
0.5 ms
SUSPEND
MGS782
Fig 7. Suspend and resume timing for powered-off application. Table 12: Pin A0 DATA[15:0] SUSPEND WAKEUP INT RESET CS RD WR XTAL1 CLKOUT
[1]
Pin states in powered-off application Type I I/O (three-state) O I O I I I I I O ISP1181B drives logic 1 inactive powered off; internally connected to ground (logic 0) externally driven[1] to logic 1 powered off; internally connected to ground (logic 0) powered off; internally connected to ground (logic 0) powered off; internally connected to ground (logic 0) powered off; internally connected to ground (logic 0) ISP1181B drives logic 0, if the NOLAZY bit is set to logic 1 in the Hardware Configuration Register Appropriate state inactive
`Externally driven' refers to logic outside the ISP1181B.
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When external components are powered-off, it is possible that interface signals RD, WR and CS have unknown values immediately after leaving `suspend' state. To prevent corruption of its internal registers, ISP1181B enables a locking mechanism once suspend is enabled. After wake-up from `suspend' state, all internal registers except the Unlock Register are write-protected. A special unlock operation is needed to re-enable write access. This prevents data corruption during power-up of external components. Figure 8 shows a typical bus-powered modem application using ISP1181B in powered-off mode. The SUSPEND output is used to switch off power to the microcontroller and other external circuits during `suspend' state. The ISP1181B is woken up via the USB bus (global resume) or by the ring detection circuit on the telephone line.
VBUS
VCC RST VCC
8031
USB
D+ D-
ISP1181B
SUSPEND WAKEUP RING DETECTION LINE
004aaa139
Fig 8. SUSPEND and WAKEUP signals in a powered-off modem application.
11.2 Resume conditions
Wake-up from `suspend' state is initiated either by the USB host or by the application:
* USB host: drives a K-state on the USB bus (global resume) * Application: remote wake-up via a HIGH level on input WAKEUP or a LOW level
on input CS (if enabled via bit WKUPCS in the Hardware Configuration Register). Wake-up on CS will work only if VBUS is present. The steps of a wake-up sequence are as follows: 1. The internal oscillator and the PLL multiplier are re-enabled. When stabilized, the clock signals are routed to all internal circuits of the ISP1181B. 2. The SUSPEND output is de-asserted and the RESUME bit in the Interrupt Register is set. This will generate an interrupt if bit IERESUME in the Interrupt Enable Register is set. 3. Maximum 15 ms after starting the wake-up sequence the ISP1181B resumes its normal functionality. 4. In case of a remote wake-up ISP1181B drives a K-state on the USB bus for 10 ms. 5. Following the de-assertion of output SUSPEND, the application restores itself and other system components to normal operating mode.
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6. After wake-up the internal registers of ISP1181B are write-protected to prevent corruption by inadvertent writing during power-up of external components. The firmware must send an Unlock Device command to the ISP1181B to restore its full functionality. See Section 12.3.2 for more details.
11.3 Control bits in suspend and resume
Table 13: Register Interrupt Summary of control bits Bit SUSPND BUSTATUS Interrupt Enable Mode IESUSP SOFTCT GOSUSP Hardware Configuration EXTPUL WKUPCS PWROFF Unlock all Function a transition from `awake' to `suspend' state was detected monitors USB bus status (logic 1 = suspend); used when interrupt is serviced enables output INT to signal `suspend' state enables SoftConnect pull-up resistor to USB bus a HIGH-to-LOW transition enables `suspend' state selects internal (SoftConnect) or external pull-up resistor enables wake-up on LOW level of input CS selects powered-off mode during `suspend' state sending data AA37H unlocks the internal registers for writing after a `resume'
12. Commands and registers
The functions and registers of ISP1181B are accessed via commands, which consist of a command code followed by optional data bytes (read or write action). An overview of the available commands and registers is given in Table 14. A complete access consists of two phases: 1. Command phase: when address bit A0 = 1, the ISP1181B interprets the data on the lower byte of the bus bits D[7:0] as a command code. Commands without a data phase are executed immediately. 2. Data phase (optional): when address bit A0 = 0, the ISP1181B transfers the data on the bus to or from a register or endpoint FIFO. Multi-byte registers are accessed least significant byte/word first. The following applies for register or FIFO access in 16-bit bus mode:
* The upper byte (bits D15 to D8) in command phase or the undefined byte in data
phase are ignored.
* The access of registers is word-aligned: byte access is not allowed. * If the packet length is odd, the upper byte of the last word in an IN endpoint buffer
is not transmitted to the host. When reading from an OUT endpoint buffer, the upper byte of the last word must be ignored by the firmware. The packet length is stored in the first 2 bytes of the endpoint buffer.
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Table 14: Name
Command and register summary Destination Endpoint Configuration Register endpoint 0 OUT Endpoint Configuration Register endpoint 0 IN Endpoint Configuration Register endpoint 1 to 14 Endpoint Configuration Register endpoint 0 OUT Endpoint Configuration Register endpoint 0 IN Endpoint Configuration Register endpoint 1 to 14 Address Register Mode Register Interrupt Enable Register DMA Configuration Register DMA Counter Register resets all registers illegal: endpoint is read-only FIFO endpoint 0 IN Code (Hex) 20 21 22 to 2F 30 31 32 to 3F B6/B7 B8/B9 BA/BB C2/C3 F0/F1 F2/F3 F6 (00) 01 Transaction[1] write 1 byte[2] write 1 byte[2] write 1 byte[2][3] read 1 byte[2] read 1 byte[2] read 1 byte[2] write/read 1 byte[2] write/read 1 byte[2] write/read 2 bytes write/read 4 bytes write/read 2 bytes write/read 2 bytes N 64 bytes isochronous: N 1023 bytes interrupt/bulk: N 64 bytes N 64 bytes isochronous: N 1023 bytes[4] interrupt/bulk: N 64 bytes read 1 byte[2] read 1 byte[2] read 1 byte[2] -[3]
Initialization commands Write Control OUT Configuration Write Control IN Configuration Write Endpoint n Configuration (n = 1 to 14) Read Control OUT Configuration Read Control IN Configuration Read Endpoint n Configuration (n = 1 to 14) Write/Read Device Address Write/Read Mode Register Write/Read Interrupt Enable Register Write/Read DMA Configuration Write/Read DMA Counter Reset Device Data flow commands Write Control OUT Buffer Write Control IN Buffer Write Endpoint n Buffer (n = 1 to 14) Read Control OUT Buffer Read Control IN Buffer Read Endpoint n Buffer (n = 1 to 14) Stall Control OUT Endpoint Stall Control IN Endpoint Stall Endpoint n (n = 1 to 14) Read Control OUT Status Read Control IN Status Read Endpoint n Status (n = 1 to 14) Validate Control OUT Buffer Validate Control IN Buffer
Write/Read Hardware Configuration Hardware Configuration Register
FIFO endpoint 1 to 14 (IN endpoints 02 to 0F only) FIFO endpoint 0 OUT illegal: endpoint is write-only FIFO endpoint 1 to 14 (OUT endpoints only) Endpoint 0 OUT Endpoint 0 IN Endpoint 1 to 14 Endpoint Status Register endpoint 0 OUT Endpoint Status Register endpoint 0 IN Endpoint Status Register n endpoint 1 to 14 illegal: IN endpoints only[5] FIFO endpoint 0 IN[5] 10 (11) 12 to 1F
40 41 42 to 4F 50 51 52 to 5F (60) 61
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Table 14: Name
Command and register summary...continued Destination Code (Hex) Transaction[1] -[3] -[3] [3]
Validate Endpoint n Buffer (n = 1 to 14) Clear Control OUT Buffer Clear Control IN Buffer Clear Endpoint n Buffer (n = 1 to 14) Unstall Control OUT Endpoint Unstall Control IN Endpoint Unstall Endpoint n (n = 1 to 14) Check Control OUT Status[7] Check Control IN Status[7] Check Endpoint n Status (n = 1 to 14)[7] Acknowledge Setup General commands Read Control OUT Error Code Read Control IN Error Code Read Endpoint n Error Code (n = 1 to 14) Unlock Device Write/Read Scratch Register Read Frame Number Read Chip ID Read Interrupt Register
[1] [2] [3] [4] [5] [6] [7]
FIFO endpoint 1 to 14 (IN endpoints 62 to 6F only)[5] FIFO endpoint 0 OUT illegal[6] FIFO endpoint 1 to 14 (OUT endpoints only)[6] Endpoint 0 OUT Endpoint 0 IN Endpoint 1 to 14 Endpoint Status Image Register endpoint 0 OUT Endpoint Status Image Register endpoint 0 IN Endpoint Status Image Register n endpoint 1 to 14 Endpoint 0 IN and OUT Error Code Register endpoint 0 OUT Error Code Register endpoint 0 IN Error Code Register endpoint 1 to 14 all registers with write access Scratch Register Frame Number Register Chip ID Register Interrupt Register 70 (71) 72 to 7F 80 81 82 to 8F D0 D1 D2 to DF F4 A0 A1 A2 to AF B0 B2/B3 B4 B5 C0
read 1 byte[2] read 1 byte[2] read 1 byte[2] -[3] read 1 byte[2] read 1 byte[2] read 1 byte[2] write 2 bytes write/read 2 bytes read 1 or 2 bytes read 2 bytes read 4 bytes
With N representing the number of bytes, the number of words for 16-bit bus width is: (N + 1) DIV 2. When accessing an 8-bit register in 16-bit mode, the upper byte is invalid. In 8-bit bus mode this command requires more time to complete than other commands. See Table 59. During isochronous transfer in 16-bit mode, because N 1023, the firmware must take care of the upper byte. Validating an OUT endpoint buffer causes unpredictable behavior of ISP1181B. Clearing an IN endpoint buffer causes unpredictable behavior of ISP1181B. Reads a copy of the Status Register: executing this command does not clear any status bits or interrupt bits.
12.1 Initialization commands
Initialization commands are used during the enumeration process of the USB network. These commands are used to configure and enable the embedded endpoints. They also serve to set the USB assigned address of ISP1181B and to perform a device reset.
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12.1.1
Write/Read Endpoint Configuration This command is used to access the Endpoint Configuration Register (ECR) of the target endpoint. It defines the endpoint type (isochronous or bulk/interrupt), direction (OUT/IN), FIFO size and buffering scheme. It also enables the endpoint FIFO. The register bit allocation is shown in Table 15. A bus reset will disable all endpoints. The allocation of FIFO memory only takes place after all 16 endpoints have been configured in sequence (from endpoint 0 OUT to endpoint 14). Although the control endpoints have fixed configurations, they must be included in the initialization sequence and be configured with their default values (see Table 4). Automatic FIFO allocation starts when endpoint 14 has been configured. Remark: If any change is made to an endpoint configuration which affects the allocated memory (size, enable/disable), the FIFO memory contents of all endpoints becomes invalid. Therefore, all valid data must be removed from enabled endpoints before changing the configuration. Code (Hex): 20 to 2F -- write (control OUT, control IN, endpoint 1 to 14) Code (Hex): 30 to 3F -- read (control OUT, control IN, endpoint 1 to 14) Transaction -- write/read 1 byte
Table 15: Bit Symbol Reset Access
Endpoint Configuration Register: bit allocation 7 FIFOEN 0 R/W 6 EPDIR 0 R/W Table 16: Bit 7 6 5 4 3 to 0 5 DBLBUF 0 R/W 4 FFOISO 0 R/W 0 R/W 0 R/W 3 2 FFOSZ[3:0] 0 R/W 0 R/W 1 0
Endpoint Configuration Register: bit description Symbol FIFOEN EPDIR DBLBUF FFOISO FFOSZ[3:0] Description A logic 1 indicates an enabled FIFO with allocated memory. A logic 0 indicates a disabled FIFO (no bytes allocated). This bit defines the endpoint direction (0 = OUT, 1 = IN). It also determines the DMA transfer direction (0 = read, 1 = write). A logic 1 indicates that this endpoint has double buffering. A logic 1 indicates an isochronous endpoint. A logic 0 indicates a bulk or interrupt endpoint. Selects the FIFO size according to Table 5
12.1.2
Write/Read Device Address This command is used to set the USB assigned address in the Address Register and enable the USB device. The Address Register bit allocation is shown in Table 17. A USB bus reset sets the device address to 00H (internally) and enables the device. The value of the Address Register (accessible by the micro) is not altered by the bus reset. In response to the standard USB request Set Address the firmware must issue a Write Device Address command, followed by sending an empty packet to the host. The new device address is activated when the host acknowledges the empty packet. Code (Hex): B6/B7 -- write/read Address Register Transaction -- write/read 1 byte
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Table 17: Bit Symbol Reset Access
Address Register: bit allocation 7 DEVEN 0 R/W 0 R/W Table 18: Bit 7 6 to 0 0 R/W 0 R/W 6 5 4 3 DEVADR[6:0] 0 R/W 0 R/W 0 R/W 0 R/W 2 1 0
Address Register: bit description Symbol DEVEN DEVADR[6:0] Description A logic 1 enables the device. This field specifies the USB device address.
12.1.3
Write/Read Mode Register This command is used to access the ISP1181B Mode Register, which consists of 1 byte (bit allocation: see Table 19). In 16-bit bus mode the upper byte is ignored. The Mode Register controls the DMA bus width, resume and suspend modes, interrupt activity and SoftConnect operation. It can be used to enable debug mode, where all errors and Not Acknowledge (NAK) conditions will generate an interrupt. Code (Hex): B8/B9 -- write/read Mode Register Transaction -- write/read 1 byte
Table 19: Bit Symbol Reset Access
[1]
Mode Register: bit allocation 7 DMAWD 0[1] R/W 6 reserved 0 R/W 5 GOSUSP 0 R/W 4 reserved 0 R/W 3 INTENA 0[1] R/W 2 DBGMOD 0[1] R/W 1 reserved 0[1] R/W 0 SOFTCT 0[1] R/W
Unchanged by a bus reset.
Table 20: Bit 7
Mode Register: bit description Symbol DMAWD Description A logic 1 selects 16-bit DMA bus width (bus configuration modes 0 and 2). A logic 0 selects 8-bit DMA bus width. Bus reset value: unchanged. reserved Writing a logic 1 followed by a logic 0 will activate `suspend' mode. reserved A logic 1 enables all interrupts. Bus reset value: unchanged.
6 5 4 3
GOSUSP INTENA
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Mode Register: bit description...continued Symbol DBGMOD Description A logic 1 enables debug mode. where all NAKs and errors will generate an interrupt. A logic 0 selects normal operation, where interrupts are generated on every ACK (bulk endpoints) or after every data transfer (isochronous endpoints). Bus reset value: unchanged. reserved A logic 1 enables SoftConnect (see Section 7.4). This bit is ignored if EXTPUL = 1 in the Hardware Configuration Register (see Table 21). Bus reset value: unchanged.
Table 20: Bit 2
1 0
SOFTCT
12.1.4
Write/Read Hardware Configuration This command is used to access the Hardware Configuration Register, which consists of 2 bytes. The first (lower) byte contains the device configuration and control values, the second (upper) byte holds the clock control bits and the clock division factor. The bit allocation is given in Table 21. A bus reset will not change any of the programmed bit values. The Hardware Configuration Register controls the connection to the USB bus, clock activity and power supply during `suspend' state, output clock frequency, DMA operating mode and pin configurations (polarity, signalling mode). Code (Hex): BA/BB -- write/read Hardware Configuration Register Transaction -- write/read 2 bytes
Table 21: Bit Symbol Reset Access Bit Symbol Reset Access
Hardware Configuration Register: bit allocation 15 reserved 0 R/W 7 DAKOLY 0 R/W 14 EXTPUL 0 R/W 6 DRQPOL 1 R/W Table 22: Bit 15 14 13 NOLAZY 1 R/W 5 DAKPOL 0 R/W 12 CLKRUN 0 R/W 4 EOTPOL 0 R/W 0 R/W 3 WKUPCS 0 R/W 0 R/W 2 PWROFF 0 R/W 11 10 CKDIV[3:0] 1 R/W 1 INTLVL 0 R/W 1 R/W 0 INTPOL 0 R/W 9 8
Hardware Configuration Register: bit description Symbol EXTPUL Description reserved A logic 1 indicates that an external 1.5 k pull-up resistor is used on pin D+ and that SoftConnect is not used. Bus reset value: unchanged. A logic 1 disables output on pin CLKOUT of the LazyClock frequency (100 50 % kHz) during `suspend' state. A logic 0 causes pin CLKOUT to switch to LazyClock output after approximately 2 ms delay, following the setting of bit GOSUSP in the Mode Register. Bus reset value: unchanged.
13
NOLAZY
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Hardware Configuration Register: bit description...continued Symbol CLKRUN Description A logic 1 indicates that the internal clocks are always running, even during `suspend' state. A logic 0 switches off the internal oscillator and PLL, when they are not needed. During `suspend' state this bit must be made logic 0 to meet the suspend current requirements. The clock is stopped after a delay of approximately 2 ms, following the setting of bit GOSUSP in the Mode Register. Bus reset value: unchanged. This field specifies the clock division factor N, which controls the clock frequency on output CLKOUT. The output frequency in MHz is given by 48 ( N + 1 ) . The clock frequency range is 3 to 48 MHz (N = 0 to 15). with a reset value of 12 MHz (N = 3). The hardware design guarantees no glitches during frequency change. Bus reset value: unchanged. A logic 1 selects DACK-only DMA mode. A logic 0 selects 8237 compatible DMA mode. Bus reset value: unchanged. Selects DREQ signal polarity (0 = active LOW, 1 = active HIGH). Bus reset value: unchanged. Selects DACK signal polarity (0 = active LOW, 1 = active HIGH). Bus reset value: unchanged. Selects EOT signal polarity (0 = active LOW, 1 = active HIGH). Bus reset value: unchanged. A logic 1 enables remote wake-up via a LOW level on input CS (For wake-up on CS to work, VBUS must be present). Bus reset value: unchanged. A logic 1 enables powering-off during `suspend' state. Output SUSPEND is configured as a power switch control signal for external devices (HIGH during `suspend'). This value should always be initialized to logic 1. Bus reset value: unchanged. Selects the interrupt signalling mode on output INT (0 = level, 1 = pulsed). In pulsed mode an interrupt produces an 166 ns pulse. See Section 13 for details. Bus reset value: unchanged. Selects INT signal polarity (0 = active LOW, 1 = active HIGH). Bus reset value: unchanged.
Table 22: Bit 12
11 to 8
CKDIV[3:0]
7 6 5 4 3
DAKOLY DRQPOL DAKPOL EOTPOL WKUPCS
2
PWROFF
1
INTLVL
0
INTPOL
12.1.5
Write/Read Interrupt Enable Register This command is used to individually enable/disable interrupts from all endpoints, as well as interrupts caused by events on the USB bus (SOF, SOF lost, EOT, suspend, resume, reset). A bus reset will not change any of the programmed bit values. The command accesses the Interrupt Enable Register, which consists of 4 bytes. The bit allocation is given in Table 23. Code (Hex): C2/C3 -- write/read Interrupt Enable Register Transaction -- write/read 4 bytes
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Table 23: Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access
Interrupt Enable Register: bit allocation 31 0 R/W 23 IEP14 0 R/W 15 IEP6 0 R/W 7 reserved 0 R/W 30 0 R/W 22 IEP13 0 R/W 14 IEP5 0 R/W 6 SP_IEEOT 0 R/W Table 24: Bit 31 to 24 23 to 10 9 8 7 6 5 4 3 2 1 0 29 0 R/W 21 IEP12 0 R/W 13 IEP4 0 R/W 5 IEPSOF 0 R/W 28 reserved 0 R/W 20 IEP11 0 R/W 12 IEP3 0 R/W 4 IESOF 0 R/W 0 R/W 19 IEP10 0 R/W 11 IEP2 0 R/W 3 IEEOT 0 R/W 0 R/W 18 IEP9 0 R/W 10 IEP1 0 R/W 2 IESUSP 0 R/W 0 R/W 17 IEP8 0 R/W 9 IEP0IN 0 R/W 1 IERESM 0 R/W 0 R/W 16 IEP7 0 R/W 8 IEP0OUT 0 R/W 0 IERST 0 R/W 27 26 25 24
Interrupt Enable Register: bit description Symbol IEP0IN IEP0OUT SP_IEEOT IEPSOF IESOF IEEOT IESUSP IERESM IERST Description reserved; must write logic 0 A logic 1 enables interrupts from the control IN endpoint. A logic 1 enables interrupts from the control OUT endpoint. reserved A logic 1 enables interrupt upon detection of a short packet. A logic 1 enables 1 ms interrupts upon detection of Pseudo SOF. A logic 1 enables interrupt upon SOF detection. A logic 1 enables interrupt upon EOT detection. A logic 1 enables interrupt upon detection of `suspend' state. A logic 1 enables interrupt upon detection of a `resume' state. A logic 1 enables interrupt upon detection of a bus reset.
IEP14 to IEP1 A logic 1 enables interrupts from the indicated endpoint.
12.1.6
Write/Read DMA Configuration This command defines the DMA configuration of ISP1181B and enables/disables DMA transfers. The command accesses the DMA Configuration Register, which consists of 2 bytes. The bit allocation is given in Table 25. A bus reset will clear bit DMAEN (DMA disabled), all other bits remain unchanged. Code (Hex): F0/F1 -- write/read DMA Configuration Transaction -- write/read 2 bytes
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Table 25: Bit Symbol Reset Access Bit Symbol Reset Access
[1]
DMA Configuration Register: bit allocation 15 CNTREN 0[1] R/W 7 0[1] R/W 14 SHORTP 0[1] R/W 6 EPDIX[3:0] 0[1] R/W 0[1] R/W 0[1] R/W 0[1] R/W 5 0[1] R/W 4 0[1] R/W 3 DMAEN 0 R/W 13 12 11 reserved 0[1] R/W 2 reserved 0 R/W 0[1] R/W 1 0[1] R/W 0[1] R/W 0 0[1] R/W 10 9 8
BURSTL[1:0]
Unchanged by a bus reset.
Table 26: Bit 15
DMA Configuration Register: bit description Symbol CNTREN Description A logic 1 enables the generation of an EOT condition, when the DMA Counter Register reaches zero. Bus reset value: unchanged. A logic 1 enables short/empty packet mode. When receiving (OUT endpoint) a short/empty packet an EOT condition is generated. When transmitting (IN endpoint) this bit should be cleared. Bus reset value: unchanged. reserved Indicates the destination endpoint for DMA, see Table 7. Writing a logic 1 enables DMA transfer, a logic 0 forces the end of an ongoing DMA transfer. Reading this bit indicates whether DMA is enabled (0 = DMA stopped, 1 = DMA enabled). This bit is cleared by a bus reset. reserved Selects the DMA burst length: 00 -- single-cycle mode (1 byte) 01 -- burst mode (4 bytes) 10 -- burst mode (8 bytes) 11 -- burst mode (16 bytes). Bus reset value: unchanged.
14
SHORTP
13 to 8 7 to 4 3
EPDIX[3:0] DMAEN
2 1 to 0
BURSTL[1:0]
12.1.7
Write/Read DMA Counter This command accesses the DMA Counter Register, which consists of 2 bytes. The bit allocation is given in Table 27. Writing to the register sets the number of bytes for a DMA transfer. Reading the register returns the number of remaining bytes in the current transfer. A bus reset will not change the programmed bit values. The internal DMA counter is automatically reloaded from the DMA Counter Register when DMA is re-enabled (DMAEN = 1). See Section 12.1.6 for more details. Code (Hex): F2/F3 -- write/read DMA Counter Register Transaction -- write/read 2 bytes
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Table 27: Bit Symbol Reset Access Bit Symbol Reset Access
DMA Counter Register: bit allocation 15 0 R/W 7 0 R/W 14 0 R/W 6 0 R/W Table 28: Bit 15 to 8 7 to 0 13 0 R/W 5 0 R/W 12 0 R/W 4 0 R/W 11 0 R/W 3 0 R/W 10 0 R/W 2 0 R/W 9 0 R/W 1 0 R/W 8 0 R/W 0 0 R/W DMACRH[7:0]
DMACRL[7:0]
DMA Counter Register: bit description Symbol DMACRL[7:0] Description DMA Counter Register (low byte) DMACRH[7:0] DMA Counter Register (high byte)
12.1.8
Reset Device This command resets the ISP1181B in the same way as an external hardware reset via input RESET. All registers are initialized to their `reset' values. Code (Hex): F6 -- reset the device Transaction -- none
12.2 Data flow commands
Data flow commands are used to manage the data transmission between the USB endpoints and the system microcontroller. Much of the data flow is initiated via an interrupt to the microcontroller. The data flow commands are used to access the endpoints and determine whether the endpoint FIFOs contain valid data. Remark: The IN buffer of an endpoint contains input data for the host, the OUT buffer receives output data from the host. 12.2.1 Write/Read Endpoint Buffer This command is used to access endpoint FIFO buffers for reading or writing. First, the buffer pointer is reset to the beginning of the buffer. Following the command, a maximum of (N + 2) bytes can be written or read, N representing the size of the endpoint buffer. For 16-bit access the maximum number of words is (M + 1), with M given by (N + 1) DIV 2. After each read/write action the buffer pointer is automatically incremented by 1 (8-bit bus width) or by 2 (16-bit bus width). In DMA access the first 2 bytes or the first word (the packet length) are skipped: transfers start at the third byte or the second word of the endpoint buffer. When reading, the ISP1181B can detect the last byte/word via the EOP condition. When writing to a bulk/interrupt endpoint, the endpoint buffer must be completely filled before sending the data to the host. Exception: when a DMA transfer is stopped by an external EOT condition, the current buffer content (full or not) is sent to the host. Remark: Reading data after a Write Endpoint Buffer command or writing data after a Read Endpoint Buffer command data will cause unpredictable behavior of ISP1181B.
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Code (Hex): 01 to 0F -- write (control IN, endpoint 1 to 14) Code (Hex): 10, 12 to 1F -- read (control OUT, endpoint 1 to 14) Transaction -- write/read maximum (N + 2) bytes (isochronous endpoint: N 1023, bulk/interrupt endpoint: N 32) The data in the endpoint FIFO must be organized as shown in Table 29. Examples of endpoint FIFO access are given in Table 30 (8-bit bus) and Table 31 (16-bit bus).
Table 29: Byte # (8-bit bus) 0 1 2 3 ... (N + 1) Table 30: A0 1 0 0 0 0 0 0 ... Table 31: A0 1 0 0 0 ... Endpoint FIFO organization Word # (16-bit bus) 0 (lower byte) 0 (upper byte) 1 (lower byte) 1 (upper byte) ... M = (N + 1) DIV 2 Description packet length (lower byte) packet length (upper byte) data byte 1 data byte 2 ... data byte N
Example of endpoint FIFO access (8-bit bus width) Phase command data data data data data data ... Bus lines D[7:0] D[7:0] D[7:0] D[7:0] D[7:0] D[7:0] D[7:0] ... Byte # 0 1 2 3 4 5 ... Description command code (00H to 1FH) packet length (lower byte) packet length (upper byte) data byte 1 data byte 2 data byte 3 data byte 4 ...
Example of endpoint FIFO access (16-bit bus width) Phase command data data data ... Bus lines D[7:0] D[15:8] D[15:0] D[15:0] D[15:0] ... Word # 0 1 2 ... Description command code (00H to 1FH) ignored packet length data word 1 (data byte 2, data byte 1) data word 2 (data byte 4, data byte 3) ...
Remark: There is no protection against writing or reading past a buffer's boundary, against writing into an OUT buffer or reading from an IN buffer. Any of these actions could cause an incorrect operation. Data residing in an OUT buffer are only meaningful after a successful transaction. Exception: during DMA access of a double-buffered endpoint, the buffer pointer automatically points to the secondary buffer after reaching the end of the primary buffer.
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12.2.2
Read Endpoint Status This command is used to read the status of an endpoint FIFO. The command accesses the Endpoint Status Register, the bit allocation of which is shown in Table 32. Reading the Endpoint Status Register will clear the interrupt bit set for the corresponding endpoint in the Interrupt Register (see Table 48). All bits of the Endpoint Status Register are read-only. Bit EPSTAL is controlled by the Stall/Unstall commands and by the reception of a SETUP token (see Section 12.2.3). Code (Hex): 50 to 5F -- read (control OUT, control IN, endpoint 1 to 14) Transaction -- read 1 byte
Table 32: Bit Symbol Reset Access
Endpoint Status Register: bit allocation 7 EPSTAL 0 R 6 EPFULL1 0 R Table 33: Bit 7 5 EPFULL0 0 R 4 DATA_PID 0 R 3 OVER WRITE 0 R 2 SETUPT 0 R 1 CPUBUF 0 R 0 reserved 0 R
Endpoint Status Register: bit description Symbol EPSTAL Description This bit indicates whether the endpoint is stalled or not (1 = stalled, 0 = not stalled). Set to logic 1 by a Stall Endpoint command, cleared to logic 0 by an Unstall Endpoint command. The endpoint is automatically unstalled upon reception of a SETUP token.
6 5 4 3
EPFULL1 EPFULL0 DATA_PID OVERWRITE
A logic 1 indicates that the secondary endpoint buffer is full. A logic 1 indicates that the primary endpoint buffer is full. This bit indicates the data PID of the next packet (0 = DATA PID, 1 = DATA1 PID). This bit is set by hardware, a logic 1 indicating that a new Setup packet has overwritten the previous setup information, before it was acknowledged or before the endpoint was stalled. This bit is cleared by reading, if writing the setup data has finished. Firmware must check this bit before sending an Acknowledge Setup command or stalling the endpoint. Upon reading a logic 1 the firmware must stop ongoing setup actions and wait for a new Setup packet.
2 1 0
SETUPT CPUBUF -
A logic 1 indicates that the buffer contains a Setup packet. This bit indicates which buffer is currently selected for CPU access (0 = primary buffer, 1 = secondary buffer). reserved
12.2.3
Stall Endpoint/Unstall Endpoint These commands are used to stall or unstall an endpoint. The commands modify the content of the Endpoint Status Register (see Table 32). A stalled control endpoint is automatically unstalled when it receives a SETUP token, regardless of the packet content. If the endpoint should stay in its stalled state, the microcontroller can re-stall it with the Stall Endpoint command.
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When a stalled endpoint is unstalled (either by the Unstall Endpoint command or by receiving a SETUP token), it is also re-initialized. This flushes the buffer: if it is an OUT buffer it waits for a DATA 0 PID, if it is an IN buffer it writes a DATA 0 PID. Code (Hex): 40 to 4F -- stall (control OUT, control IN, endpoint 1 to 14) Code (Hex): 80 to 8F -- unstall (control OUT, control IN, endpoint 1 to 14) Transaction -- none 12.2.4 Validate Endpoint Buffer This command signals the presence of valid data for transmission to the USB host, by setting the Buffer Full flag of the selected IN endpoint. This indicates that the data in the buffer is valid and can be sent to the host, when the next IN token is received. For a double-buffered endpoint this command switches the current FIFO for CPU access. Remark: For special aspects of the control IN endpoint see Section 9.5. Code (Hex): 61 to 6F -- validate endpoint buffer (control IN, endpoint 1 to 14) Transaction -- none 12.2.5 Clear Endpoint Buffer This command unlocks and clears the buffer of the selected OUT endpoint, allowing the reception of new packets. Reception of a complete packet causes the Buffer Full flag of an OUT endpoint to be set. Any subsequent packets are refused by returning a NAK condition, until the buffer is unlocked using this command. For a double-buffered endpoint this command switches the current FIFO for CPU access. Remark: For special aspects of the control OUT endpoint see Section 9.5. Code (Hex): 70, 72 to 7F -- clear endpoint buffer (control OUT, endpoint 1 to 14) Transaction -- none 12.2.6 Check Endpoint Status This command is used to check the status of the selected endpoint FIFO without clearing any status or interrupt bits. The command accesses the Endpoint Status Image Register, which contains a copy of the Endpoint Status Register. The bit allocation of the Endpoint Status Image Register is shown in Table 34. Code (Hex): D0 to DF -- check status (control OUT, control IN, endpoint 1 to 14) Transaction -- write/read 1 byte
Table 34: Bit Symbol Reset Access Endpoint Status Image Register: bit allocation 7 EPSTAL 0 R 6 EPFULL1 0 R 5 EPFULL0 0 R 4 DATA_PID 0 R 3 OVER WRITE 0 R 2 SETUPT 0 R 1 CPUBUF 0 R 0 reserved 0 R
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Endpoint Status Image Register: bit description Symbol EPSTAL EPFULL1 EPFULL0 DATA_PID OVERWRITE Description This bit indicates whether the endpoint is stalled or not (1 = stalled, 0 = not stalled). A logic 1 indicates that the secondary endpoint buffer is full. A logic 1 indicates that the primary endpoint buffer is full. This bit indicates the data PID of the next packet (0 = DATA0 PID, 1 = DATA1 PID). This bit is set by hardware, a logic 1 indicating that a new Setup packet has overwritten the previous setup information, before it was acknowledged or before the endpoint was stalled. This bit is cleared by reading, if writing the setup data has finished. Firmware must check this bit before sending an Acknowledge Setup command or stalling the endpoint. Upon reading a logic 1 the firmware must stop ongoing setup actions and wait for a new Setup packet.
Table 35: Bit 7 6 5 4 3
2 1 0
SETUPT CPUBUF -
A logic 1 indicates that the buffer contains a Setup packet. This bit indicates which buffer is currently selected for CPU access (0 = primary buffer, 1 = secondary buffer). reserved
12.2.7
Acknowledge Setup This command acknowledges to the host that a SETUP packet was received. The arrival of a SETUP packet disables the Validate Buffer and Clear Buffer commands for the control IN and OUT endpoints. The microcontroller needs to re-enable these commands by sending an Acknowledge Setup command, see Section 9.5. Code (Hex): F4 -- acknowledge setup Transaction -- none
12.3 General commands
12.3.1 Read Endpoint Error Code This command returns the status of the last transaction of the selected endpoint, as stored in the Error Code Register. Each new transaction overwrites the previous status information. The bit allocation of the Error Code Register is shown in Table 36. Code (Hex): A0 to AF -- read error code (control OUT, control IN, endpoint 1 to 14) Transaction -- read 1 byte
Table 36: Bit Symbol Reset Access Error Code Register: bit allocation 7 UNREAD 0 R 6 DATA01 0 R 5 reserved 0 R 0 R 0 R 4 3 ERROR[3:0] 0 R 0 R 2 1 0 RTOK 0 R
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Error Code Register: bit description Symbol UNREAD DATA01 ERROR[3:0] RTOK Description A logic 1 indicates that a new event occurred before the previous status was read. This bit indicates the PID type of the last successfully received or transmitted packet (0 = DATA0 PID, 1 = DATA1 PID). reserved Error code. For error description, see Table 38. A logic 1 indicates that data was received or transmitted successfully.
Table 37: Bit 7 6 5 4 to 1 0
Table 38: Error code (Binary) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Transaction error codes Description no error PID encoding error; bits 7 to 4 are not the inverse of bits 3 to 0 PID unknown; encoding is valid, but PID does not exist unexpected packet; packet is not of the expected type (token, data, or acknowledge), or is a SETUP token to a non-control endpoint token CRC error data CRC error time-out error babble error unexpected end-of-packet sent or received NAK (Not AcKnowledge) sent Stall; a token was received, but the endpoint was stalled overflow; the received packet was larger than the available buffer space sent empty packet (ISO only) bit stuffing error sync error wrong (unexpected) toggle bit in DATA PID; data was ignored
12.3.2
Unlock Device This command unlocks the ISP1181B from write-protection mode after a `resume'. In `suspend' state all registers and FIFOs are write-protected to prevent data corruption by external devices during a `resume'. Also, the register access for reading is possible only after the `Unlock Device' command is executed. After waking up from `suspend' state, the firmware must unlock the registers and FIFOs via this command, by writing the unlock code (AA37H) into the Lock Register (8-bit bus: lower byte first). The bit allocation of the Lock Register is given in Table 39. Code (Hex): B0 -- unlock the device Transaction -- write 2 bytes (unlock code)
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Table 39: Bit Symbol Reset Access Bit Symbol Reset Access
Lock Register: bit allocation 15 1 W 7 0 W 14 0 W 6 0 W Table 40: Bit 15 to 0 13 1 W 5 1 W 12 0 W 4 1 W 11 1 W 3 0 W 10 0 W 2 1 W 9 1 W 1 1 W 8 0 W 0 1 W UNLOCKH[7:0] = AAH
UNLOCKL[7:0] = 37H
Error Code Register: bit description Symbol UNLOCK[15:0] Description Sending data AA37H unlocks the internal registers and FIFOs for writing, following a `resume'.
12.3.3
Write/Read Scratch Register This command accesses the 16-bit Scratch Register, which can be used by the firmware to save and restore information, e.g. the device status before powering down in `suspend' state. The register bit allocation is given in Table 41. Code (Hex): B2/B3 -- write/read Scratch Register Transaction -- write/read 2 bytes
Table 41: Bit Symbol Reset Access Bit Symbol Reset Access
Scratch Information Register: bit allocation 15 reserved 0 R/W 7 0 R/W 0 R/W 6 0 R/W Table 42: Bit 15 14 to 8 7 to 0 0 R/W 5 0 R/W 0 R/W 4 SFIRL[7:0] 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 14 13 12 11 SFIRH[6:0] 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 10 9 8
Scratch Information Register: bit description Symbol SFIRH[6:0] SFIRL[7:0] Description reserved; must be logic 0 Scratch Information Register (high byte) Scratch Information Register (low byte)
12.3.4
Read Frame Number This command returns the frame number of the last successfully received SOF. It is followed by reading one or two bytes from the Frame Number Register, containing the frame number (lower byte first). The Frame Number Register is shown in Table 43. Remark: After a bus reset, the value of the Frame Number Register is undefined.
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Code (Hex): B4 -- read frame number Transaction -- read 1 or 2 bytes
Table 43: Bit Symbol Reset[1] Access Bit Symbol Reset[1] Access
[1]
Frame Number Register: bit allocation 15 0 R 7 0 R 14 0 R 6 0 R 13 reserved 0 R 5 0 R 0 R 4 SOFRL[7:0] 0 R 0 R 0 R 0 R 0 R 0 R 3 0 R 2 12 11 10 9 SOFRH[2:0] 0 R 1 0 R 0 8
Reset value undefined after a bus reset.
Table 44: A0 1 0 0 Table 45: A0 1 0
Example of Frame Number Register access (8-bit bus width) Phase command data data Bus lines D[7:0] D[7:0] D[7:0] Byte # 0 1 Description command code (B4H) frame number (lower byte) frame number (upper byte)
Example of Frame Number Register access (16-bit bus width) Phase command data Bus lines D[7:0] D[15:8] D[15:0] Word # 0 Description command code (B4H) ignored frame number
12.3.5
Read Chip ID This command reads the chip identification code and hardware version number. The firmware must check this information to determine the supported functions and features. This command accesses the Chip ID Register, which is shown in Table 46. Code (Hex): B5 -- read chip ID Transaction -- read 2 bytes
Table 46: Bit Symbol Reset Access Bit Symbol Reset Access
Chip ID Register: bit allocation 15 14 13 12 81H R 7 R 6 R 5 R 4 42H R R R R R R R R R 3 R 2 R 1 R 0 11 10 9 8 CHIPIDH[7:0]
CHIPIDL[7:0]
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Chip ID Register: bit description Symbol CHIPIDH[7:0] CHIPIDL[7:0] Description chip ID code (81H) silicon version (42H, with 42H representing the BCD encoded version number)
Table 47: Bit 15 to 8 7 to 0
12.3.6
Read Interrupt Register This command indicates the sources of interrupts as stored in the 4-byte Interrupt Register. Each individual endpoint has its own interrupt bit. The bit allocation of the Interrupt Register is shown in Table 48. Bit BUSTATUS is used to verify the current bus status in the interrupt service routine. Interrupts are enabled via the Interrupt Enable Register, see Section 12.1.5. While reading the interrupt register, read all the 4 bytes completely. Code (Hex): C0 -- read interrupt register Transaction -- read 4 bytes
Table 48: Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access
Interrupt Register: bit allocation 31 0 R 23 EP14 0 R 15 EP6 0 R 7 BUSTATUS 0 R 30 0 R 22 EP13 0 R 14 EP5 0 R 6 SP_EOT 0 R Table 49: Bit 31 to 24 23 to 10 9 8 7 6 29 0 R 21 EP12 0 R 13 EP4 0 R 5 PSOF 0 R 28 reserved 0 R 20 EP11 0 R 12 EP3 0 R 4 SOF 0 R 0 R 19 EP10 0 R 11 EP2 0 R 3 EOT 0 R 0 R 18 EP9 0 R 10 EP1 0 R 2 SUSPND 0 R 0 R 17 EP8 0 R 9 EP0IN 0 R 1 RESUME 0 R 0 R 16 EP7 0 R 8 EP0OUT 0 R 0 RESET 0 R 27 26 25 24
Interrupt Register: bit description Symbol EP14 to EP1 EP0IN EP0OUT BUSTATUS SP_EOT Description reserved A logic 1 indicates the interrupt source(s): endpoint 14 to 1. A logic 1 indicates the interrupt source: control IN endpoint. A logic 1 indicates the interrupt source: control OUT endpoint. It monitors the current USB bus status (0 = awake, 1 = suspend). A logic 1 indicates that an EOT interrupt has occurred for a short packet.
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Interrupt Register: bit description...continued Symbol PSOF Description A logic 1 indicates that an interrupt is issued every 1 ms because of the Pseudo SOF; after 3 missed SOFs `suspend' state is entered. A logic 1 indicates that a SOF condition was detected. A logic 1 indicates that an internal EOT condition was generated by the DMA Counter reaching zero. A logic 1 indicates that an `awake' to `suspend' change of state was detected on the USB bus. A logic 1 indicates that a `resume' state was detected. A logic 1 indicates that a bus reset condition was detected.
Table 49: Bit 5
4 3 2 1 0
SOF EOT SUSPND RESUME RESET
13. Interrupts
Figure 9 shows the interrupt logic of the ISP1181B. Each of the indicated USB events is logged in a status bit of the Interrupt Register. Corresponding bits in the Interrupt Enable Register determine whether or not an event will generate an interrupt. Interrupts can be masked globally by means of the INTENA bit of the Mode Register (see Table 20). The active level and signalling mode of the INT output is controlled by the INTPOL and INTLVL bits of the Hardware Configuration Register (see Table 22). Default settings after reset are active LOW and level mode. When pulse mode is selected, a pulse of 166 ns is generated when the OR-ed combination of all interrupt bits changes from logic 0 to logic 1.
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interrupt register RESET SUSPND RESUME SOF EP14
. . .
. . . . . .
...
EP0IN EP0OUT EOT interrupt enable register IERST IESUSP IERESM IESOF IEP14 1 hardware configuration register INTLVL INTPOL INT
MGS772
device mode register INTENA PULSE GENERATOR
. . .
0
...
IEP0IN IEP0OUT IEEOT
Fig 9. Interrupt logic.
Bits RESET, RESUME, SP_EOT, EOT and SOF are cleared upon reading the Interrupt Register. The endpoint bits (EP0OUT to EP14) are cleared by reading the associated Endpoint Status Register. Bit BUSTATUS follows the USB bus status exactly, allowing the firmware to get the current bus status when reading the Interrupt Register. SETUP and OUT token interrupts are generated after ISP1181B has acknowledged the associated data packet. In bulk transfer mode, the ISP1181B will issue interrupts for every ACK received for an OUT token or transmitted for an IN token. In isochronous mode, an interrupt is issued upon each packet transaction. The firmware must take care of timing synchronization with the host. This can be done via the Pseudo Start-Of-Frame (PSOF) interrupt, enabled via bit IEPSOF in the Interrupt Enable Register. If a Start-Of-Frame is lost, PSOF interrupts are generated every 1 ms. This allows the firmware to keep data transfer synchronized with the host. After 3 missed SOF events the ISP1181B will enter `suspend' state. An alternative way of handling isochronous data transfer is to enable both the SOF and the PSOF interrupts and disable the interrupt for each isochronous endpoint.
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14. Power supply
The ISP1181B is powered from a single supply voltage, ranging from 4.0 to 5.5 V. An integrated voltage regulator provides a 3.3 V supply voltage for the internal logic and the USB transceiver. This voltage is available at pin Vreg(3.3) for connecting an external pull-up resistor on USB connection D+. See Figure 10. The ISP1181B can also be operated from a 3.0 to 3.6 V supply, as shown in Figure 11. In that case the internal voltage regulator is disabled and pin Vreg(3.3) must be connected to VCC.
ISP1181B
VCC VCC(3.3) Vref Vreg(3.3)
004aaa140
ISP1181B
4.0 to 5.5 V VCC VCC(3.3) Vref Vreg(3.3)
004aaa141
3.0 to 3.6 V
Fig 10. ISP1181B with a 4.0 to 5.5 V supply.
Fig 11. ISP1181B with a 3.0 to 3.6 V supply.
15. Crystal oscillator and LazyClock
The ISP1181B has a crystal oscillator designed for a 6 MHz parallel-resonant crystal (fundamental). A typical circuit is shown in Figure 12. Alternatively, an external clock signal of 6 MHz can be applied to input XTAL1, while leaving output XTAL2 open.
CLKOUT
ISP1181B
XTAL2
18 pF 6 MHz
XTAL1 18 pF
004aaa142
Fig 12. Typical oscillator circuit.
The 6 MHz oscillator frequency is multiplied to 48 MHz by an internal PLL. This frequency is used to generate a programmable clock output signal at pin CLKOUT, ranging from 3 to 48 MHz. In `suspend' state the normal CLKOUT signal is not available, because the crystal oscillator and the PLL are switched off to save power. Instead, the CLKOUT signal can be switched to the LazyClock frequency of 100 50% kHz. The oscillator operation and the CLKOUT frequency are controlled via the Hardware Configuration Register, as shown in Figure 13. The following bits are involved:
* CLKRUN switches the oscillator on and off * CLKDIV[3:0] is the division factor determining the normal CLKOUT frequency * NOLAZY controls the LazyClock signal output during `suspend' state.
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hardware configuration register CLKRUN SUSPEND
. . .
CKDIV[3:0]
enable XTAL OSC 4 6 MHz
enable 48 MHz PLL 8x
/ (N + 1)
N
1 CLKOUT 0 NOLAZY
. . .
NOLAZY
LAZYCLOCK
100 (50%) kHz
enable
MGS775
Fig 13. Oscillator and LazyClock logic.
When ISP1181B enters `suspend' state (by setting and clearing bit GOSUSP in the Mode Register), outputs SUSPEND and CLKOUT change state after approximately 2 ms delay. When NOLAZY = 0 the clock signal on output CLKOUT does not stop, but changes to the 100 50% kHz LazyClock frequency. When resuming from `suspend' state by a positive pulse on input WAKEUP, output SUSPEND is cleared and the clock signal on CLKOUT is restarted after a 0.5 ms delay. The timing of the CLKOUT signal at `suspend' and `resume' is given in Figure 14.
GOSUSP
WAKEUP 1.8 to 2.2 ms SUSPEND PLL circuit stable 3 to 4 ms CLKOUT
MGS776
0.5 ms
If enabled, the 100 50% kHz LazyClock frequency will be output on pin CLKOUT during `suspend' state.
Fig 14. CLKOUT signal timing at `suspend' and `resume'.
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16. Power-on reset
The ISP1181B has an internal power-on reset (POR) circuit. Input pin RESET can be directly connected to VCC. The clock signal on output CLKOUT starts 0.5 ms after power-on and normally requires 3 to 4 ms to stabilize. The triggering voltage of the POR circuit is 2.0 V nominal. A POR is automatically generated when VCC goes below the trigger voltage for a duration longer than 50 s.
POR VCC
(1)
2.0 V
350 s
1 ms
1 ms
0V > 50 s
t1
t2
t3
MGT026
t1: clock is running t2: BUS_CONF pins are sampled t3: registers are accessible (1) Supply voltage (5 V or 3.3 V), connected externally to pin RESET.
Fig 15. Power-on reset timing.
A hardware reset disables all USB endpoints and clears all ECRs, except for the control endpoint which is fixed and always enabled. Section 9.3 explains how to (re-)initialize the endpoints.
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17. Limiting values
Table 50: Absolute maximum ratings In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VCC VI Ilatchup Vesd Tstg Ptot
[1]
Parameter supply voltage input voltage latchup current electrostatic discharge voltage storage temperature total power dissipation
Conditions
Min -0.5 -0.5
Max +6.0 VCC + 0.5 100 2000 +150 165
Unit V V mA V C mW
VI < 0 or VI > VCC ILI < 1 A VCC = 5.5 V
[1]
-60 -
Equivalent to discharging a 100 pF capacitor via a 1.5 k resistor (Human Body Model).
17.1 Recommended operating condition
Table 51: Symbol VCC VI VI(AI/O) VO(od) Tamb Recommended operating conditions Parameter supply voltage input voltage input voltage on analog I/O pins (D+/D-) open-drain output pull-up voltage ambient temperature Conditions with regulator without regulator Min 4.0 3.0 0 0 0 -40 Typ 5.0 3.3 Max 5.5 3.6 VCC 3.6 VCC +85 Unit V V V V V C
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18. Static characteristics
Table 52: Static characteristics; supply pins VGND = 0 V; Tamb = -40 to +85 C; unless otherwise specified. Symbol Vreg(3.3) ICC ICC(susp) Parameter regulated supply voltage operating supply current suspend supply current Conditions VCC = 4.0 to 5.5 V VCC = 5.0 V; Tamb = 25C VCC = 3.3 V; Tamb = 25C VCC = 5.0 V; Tamb = 25C VCC = 3.3 V; Tamb = 25C
[1] [2] [3] For 3.3 V operation, pin Vreg(3.3) must be connected to pin VCC(3.3). In `suspend' mode the minimum voltage is 2.7 V. External loading is not included.
[1]
Min 3.0[2] -
Typ 3.3 26 22 -
Max 3.6 20[3] 70[3]
Unit V mA mA A A
Table 53: Static characteristics: digital pins VCC = 3.3 V 10% or 5.0 V 10%; VGND = 0 V; Tamb = -40 to +85 C; unless otherwise specified. Symbol Input levels VIL VIH Vth(LH) Vth(HL) Vhys Output levels VOL VOH ILI IOZ
[1]
Parameter LOW-level input voltage HIGH-level input voltage positive-going threshold voltage negative-going threshold voltage hysteresis voltage LOW-level output voltage HIGH-level output voltage input leakage current OFF-state output current
Conditions
Min 2.0 1.4 0.9 0.4
Typ -
Max 0.8 1.9 1.5 0.7 0.4 0.1 5 5
Unit V V V V V V V V A A
Schmitt trigger inputs
IOL = rated drive IOL = 20 A IOH = rated drive
[1]
2.4 -
Leakage current Open-drain outputs
Not applicable for open-drain outputs.
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Table 54: Static characteristics: analog I/O pins (D+, D-)[1] VCC = 3.3 V 10% or 5.0 V 10%; VGND = 0 V; Tamb = -40 to +85 C; unless otherwise specified. Symbol Input levels VDI VCM VIL VIH Output levels VOL VOH ILZ Capacitance CIN Resistance RPU ZDRV[2] ZINP Termination VTERM[3] termination voltage for upstream port pull-up (Rpu) 3.0[4] 3.6 V pull-up resistance on D+ driver output impedance input impedance SoftConnect = ON steady-state drive 1 29 10 2 44 k M transceiver capacitance pin to GND 20 pF LOW-level output voltage HIGH-level output voltage OFF-state leakage current RL = 1.5 k to +3.6 V RL = 15 k to GND 2.8 0.3 3.6 10 V V A differential input sensitivity differential common mode voltage LOW-level input voltage HIGH-level input voltage |VI(D+) - VI(D-)| includes VDI range 0.2 0.8 2.0 2.5 0.8 V V V V Parameter Conditions Min Typ Max Unit
Leakage current
[1] [2] [3] [4]
D+ is the USB positive data pin; D- is the USB negative data pin. Includes external resistors of 22 1% on both D+ and D-. This voltage is available at pin Vreg(3.3). In `suspend' mode the minimum voltage is 2.7 V.
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19. Dynamic characteristics
Table 55: Dynamic characteristics VCC = 3.3 V 10% or 5.0 V 10%; VGND = 0 V; Tamb = -40 to +85 C; unless otherwise specified. Symbol Reset tW(RESET) pulse width on input RESET crystal oscillator running crystal oscillator stopped Crystal oscillator fXTAL
[1]
Parameter
Conditions
Min 50 -
Typ 3[1] 6
Max -
Unit s ms MHz
crystal frequency
Dependent on the crystal oscillator start-up time.
Table 56: Dynamic characteristics: analog I/O pins (D+, D-)[1] VCC = 3.3 V 10% or 5.0 V 10%; VGND = 0 V; Tamb = -40 to +85 C; CL = 50 pF; RPU = 1.5 k on D+ to VTERM; unless otherwise specified. Symbol tFR tFF FRFM VCRS tFEOPT tFDEOP Parameter rise time fall time differential rise/fall time matching (tFR/tFF) output signal crossover voltage source EOP width see Figure 16 Conditions CL = 50 pF; 10 to 90% of |VOH - VOL| CL = 50 pF; 90 to 10% of |VOH - VOL|
[2]
Min 4 4 90 1.3 160 -2
Typ -
Max 20 20 111.11 2.0 175 +5
Unit ns ns % V ns ns
Driver characteristics
[2][3]
Data source timing
[3] [3]
source differential data-to-EOP see Figure 16 transition skew receiver data jitter tolerance for see Figure 17 consecutive transitions receiver data jitter tolerance for see Figure 17 paired transitions receiver SE0 width accepted as EOP; see Figure 16
Receiver timing tJR1 tJR2 tFEOPR tFST
[3]
-18.5 -9 82 -
-
+18.5 +9 14
ns ns ns ns
[3]
[3]
width of SE0 during differential rejected as EOP; see transition Figure 18
Test circuit: see Figure 34. Excluding the first transition from Idle state. Characterized only, not tested. Limits guaranteed by design.
[3]
[1] [2] [3]
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TPERIOD +3.3 V crossover point differential data lines crossover point extended
0V differential data to SE0/EOP skew N x TPERIOD + t DEOP source EOP width: t EOPT receiver EOP width: t EOPR
MGR776
TPERIOD is the bit duration corresponding with the USB data rate. Full-speed timing symbols have a subscript prefix `F', low-speed timings a prefix `L'.
Fig 16. Source differential data-to-EOP transition skew and EOP width.
TPERIOD +3.3 V differential data lines
0V tJR consecutive transitions N x TPERIOD + t JR1 paired transitions N x TPERIOD + t JR2 tJR1 tJR2
MGR871
TPERIOD is the bit duration corresponding with the USB data rate.
Fig 17. Receiver differential data jitter.
tFST +3.3 V differential data lines VIH(min)
0V
MGR872
Fig 18. Receiver SE0 width tolerance.
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20. Timing
20.1 Timing symbols
Table 57: Symbol Time symbols t T Signal names A C D E G I L P Q R address; DMA acknowledge (DACK) clock; command data input; data chip enable output enable instruction (program memory content); input (general) address latch enable (ALE) program store enable (PSEN, active LOW); propagation delay data output read signal (RD, active LOW); read (action); DMA request (DREQ) S W chip select write signal (WR, active LOW); write (action); pulse width U Y Logic levels H L P S V X Z logic HIGH logic LOW stop, not active (OFF) start, active (ON) valid logic level invalid logic level high-impedance (floating, three-state) undefined output (general) time cycle time (periodic signal) Legend for timing characteristics Description
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20.2 Parallel I/O timing
Table 58: Symbol Dynamic characteristics: parallel interface timing Parameter Conditions 8-bit bus Min Read timing (see Figure 19) tRHAX tAVRL tSHDZ tRHSH tRLRH tRLDV tSHRL + tRLRH tWHAX tAVWL tSHWL + tWLWH tWLWH tWHSH tDVWH tWHDZ tLH tAVLL tLLAX address hold time after RD HIGH address setup time before RD LOW data outputs high-impedance time after CS HIGH chip deselect time after RD HIGH RD pulse width data valid time after RD LOW read cycle time address hold time after WR HIGH address setup time before WR LOW write cycle time WR pulse width chip deselect time after WR HIGH data setup time before WR HIGH data hold time after WR HIGH ALE pulse width address setup time before ALE LOW address hold time after ALE LOW reading writing 3 0 0 25 90 3 0 90/180[1] 22 0 5 3 20 10 0 0 3 22 10 3 0 0 25 180 3 0 180 22 0 5 3 20 10 0 0 3 22 10 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Max 16-bit bus Min Max Unit
Write timing (see Figure 20)
ALE timing (see Figure 21)
[1]
Commands Acknowledge Setup, Clear Buffer, Validate Buffer and Write Endpoint Configuration require 180 ns to complete.
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t RHAX A0 tAVRL
t SHDZ
CS/DACK t RLRH RD t RLDV DATA
MGS787
t SHRL(1)
t RHSH
(1) For tSHRL, both CS and RD must be deasserted.
Fig 19. Parallel interface read timing (I/O and 8237 compatible DMA).
t WHAX A0 tAVWL CS/DACK t WLWH t SHWL(1) t WHSH WR t DVWH DATA
MGS789
t WHDZ
(1) For tSHWL, both CS and WR must be deasserted.
Fig 20. Parallel interface write timing (I/O and 8237 compatible DMA).
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t LH ALE t LLAX t AVLL
AD0
A0
D0
DATA
MGS790
Fig 21. ALE timing.
20.3 Access cycle timing
Table 59: Symbol Dynamic characteristics: access cycle timing Parameter Conditions Min Write command + write data (see Figure 22 and Figure 23) Tcy(WC-WD) Tcy(WD-WD) Tcy(WD-WC) cycle time for write command, then write data cycle time for write data cycle time for write data, then write command cycle time for write command, then read data cycle time for read data cycle time for read data, then write command 100[1] 90 90 205 205 205 ns ns ns 8-bit bus Max Min 16-bit bus Max Unit
Write command + read data (see Figure 24 and Figure 25) Tcy(WC-RD) Tcy(RD-RD) Tcy(RD-WC) 100[1] 90 90 205 205 205 ns ns ns
[1]
Commands Acknowledge Setup, Clear Buffer, Validate Buffer and Write Endpoint Configuration require 180 ns to complete.
DATA
command Tcy(WC-WD)
data Tcy(WD-WD)
data
WR
CS
MGT022
Fig 22. Write command + write data cycle timing.
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DATA
data Tcy(WD-WC)
command
data
WR
RD
(1)
CS
MGT025
(1) Example: read data.
Fig 23. Write data + write command cycle timing.
DATA
command
data
data
WR Tcy(WC-RD) RD Tcy(RD-RD) CS
MGT023
Fig 24. Write command + read data cycle timing.
DATA
data
command
data
WR Tcy(RD-WC) RD
(1)
CS
MGT024
(1) Example: read data.
Fig 25. Read data + write command cycle timing.
20.4 DMA timing: single-cycle mode
Table 60: Symbol Dynamic characteristics: single-cycle DMA timing Parameter Conditions Min 8237 compatible mode (see Figure 26) tASRP Tcy(DREQ)
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16-bit bus Max 40 -
Unit
DREQ off after DACK on cycle time signal DREQ
90
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Table 60: Symbol
Dynamic characteristics: single-cycle DMA timing...continued Parameter Conditions Min 8-bit bus Max 40 22 3 40 Min 25 180 180 5 3 22 0 22 16-bit bus Max 40 22 3 40 ns ns ns ns ns ns ns ns ns ns ns ns Unit
Read in DACK-only mode (see Figure 27) tASRP tASAP tASDV tAPDZ tASRP tDVAP tAPDZ tRSIH tIHAP tEOT DREQ off after DACK on DACK pulse width data valid after DACK on data hold after DACK off DREQ off after DACK on data setup before DACK off data hold after DACK off input RD/WR HIGH after DREQ on DACK off after input RD/WR HIGH EOT pulse width EOT on; DACK on; RD/WR LOW 25 90 90 5 3 22 0 22
tASAP + tAPRS DREQ on after DACK off
Write in DACK-only mode (see Figure 28) tASAP + tAPRS DREQ on after DACK off
Single-cycle EOT (see Figure 29)
tRLIS tWLIS
input EOT on after RD LOW input EOT on after WR LOW
-
22 22
-
89 89
ns ns
T cy(DREQ) t ASRP DREQ
DACK
MGS792
Fig 26. DMA timing in 8237 compatible mode.
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t ASRP DREQ t ASAP DACK
t APRS
t ASDV DATA
t APDZ
MGS793
Fig 27. DMA read timing in DACK-only mode.
t ASAP t ASRP DREQ t APRS
t DVAP DACK
t APDZ
DATA
MGS794
Fig 28. DMA write timing in DACK-only mode.
t RSIH DREQ t ASRP
(1)
t IHAP
DACK
RD/WR
(2)
t RLIS tWLIS EOT
t EOT
(3)
MGS795
(1) tASRP starts from DACK or RD/WR going LOW, whichever occurs later. (2) The RD/WR signals are not used in DACK-only DMA mode. (3) The EOT condition is considered valid if DACK, RD/WR and EOT are all active (= LOW).
Fig 29. EOT timing in single-cycle DMA mode.
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20.5 DMA timing: burst mode
Table 61: Symbol Dynamic characteristics: burst mode DMA timing Parameter Conditions Min Burst (see Figure 30) tRSIH tILRP tIHAP tIHIL input RD/WR HIGH after DREQ on DREQ off after input RD/WR LOW DACK off after input RD/WR HIGH DMA burst repeat interval (input RD/WR HIGH to LOW) EOT pulse width EOT on; DACK on; RD/WR LOW 22 0 90 60 22 0 180 60 ns ns ns ns 8-bit bus Max Min 16-bit bus Max Unit
Burst EOT (see Figure 31) tEOT 22 22 ns
tISRP tRLIS tWLIS
DREQ off after input EOT on input EOT on after RD LOW input EOT on after WR LOW
-
40 22 22
-
40 89 89
ns ns ns
t RSIH DREQ
t ILRP
t IHAP DACK t IHIL
RD/WR
MGS796
Fig 30. Burst mode DMA timing.
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t ISRP DREQ
DACK t RLIS tWLIS RD/WR t EOT(1) EOT
MGS797
(1) The EOT condition is considered valid if DACK, RD/WR and EOT are all active (= LOW).
Fig 31. EOT timing in burst mode DMA.
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21. Application information
21.1 Typical interface circuits
VCC
A1 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 H8S/2357 D13 D14 D15 CSn RD WR IRQ P1.1 DREQ0 DACK TEND AD0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 A0 ALE CS RD WR INT SUSPEND WAKEUP DREQ DACK EOT BUS_CONF1 BUS_CONF0 XTAL1 XTAL2 (1) 470 GL 6 MHz LINK LED Vreg(3.3) VCC RESET 0.1 F 0.1 F
USB upstream connector VBUS D- D+ 22 22 1 2 3 4
ISP1181B
18 pF
18 pF
004aaa143
(1) 470 assuming that VCC is 5.0 V.
Fig 32. Typical interface circuit for bus configuration mode 0 (shared ports: 16-bit PIO, 16-bit DMA).
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VCC
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 ALE
8051
PSEN RD WR IRQ
AD0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 A0 ALE CS RD WR INT SUSPEND WAKEUP DREQ DACK EOT BUS_CONF1 BUS_CONF0
LINK LED Vreg(3.3) VCC RESET 0.1 F 0.1 F
USB upstream connector VBUS D- D+ 22 22 1 2 3 4
ISP1181B
P2.3 P2.0 P2.1
XTAL1 XTAL2 470 GL (1) 6 MHz
18 pF
18 pF
BUS_REQ BUS_GNT MCU_WR MCU_RD CS1 CS2 RD WR DREQ DACK EOT D7 D6 D5 D4 D3 D2 D1 D0
CS RD WR
DMA CONTROLLER
8-BIT DMA PORT
D7 D6 D5 D4 D3 D2 D1 D0
004aaa144
(1) 470 assuming that VCC is 5.0 V.
Fig 33. Typical interface circuit for bus configuration mode 2 (shared ports: 8-bit PIO, 8-bit DMA).
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21.2 Interfacing ISP1181B with an H8S/2357 microcontroller
This section gives a summary of the ISP1181B interface with a H8S/2357 (or compatible) microcontroller. Aspects discussed are: interrupt handling, address mapping, DMA and I/O port usage for suspend and remote wake-up control. A typical interface circuit is shown in Figure 32. 21.2.1 Interrupt handling
* ISP1181B: program the Hardware Configuration register to select an active LOW
level for output INT (INTPOL = 0, see Table 21)
* H8S/2357: program the IRQ Sense Control Register (ISCRH and ISCRL) to
specify low-level sensing for the IRQ input. 21.2.2 Address mapping in H8S/2357 The H8S/2357 bus controller partitions its 16 Mbyte address space into eight areas (0 to 7) of 2 Mbyte each. The bus controller will activate one of the outputs CS0 to CS7 when external address space for the associated area is accessed. The ISP1181B can be mapped to any address area, allowing easy interfacing when the ISP1181B is the only device in that area. If in the example circuit for bus configuration mode 0 (see Figure 32) the ISP1181B is mapped to address FFFF08H (in area 7), output CS7 of the H8S/2357 can be directly connected to input CS of the ISP1181B. The external bus specifications, bus width, number of access states and number of program wait states can be programmed for each address area. The recommended settings of H8S/2357 for interfacing the ISP1181B are:
* 8-bit bus in Bus Width Control Register (ABWCR) * enable wait states in Access State Control Register (ASTCR) * 1 program wait state in the Wait Control Register (WCRH and WCRL).
21.2.3 Using DMA The ISP1181B can be configured for several methods of DMA with the H8S/2357 and other devices. The interface circuit in Figure 32 shows an example of the ISP1181B working with the H8S/2357 in single-address DACK-only DMA mode. External devices are not shown. For single-address DACK-only mode, firmware must program the following settings:
* ISP1181B:
- program the DMA Counter register with the total transfer byte count - program the Hardware Configuration Register to select active level LOW for DREQ and DACK - select the target endpoint and transfer direction - select DACK-only mode and enable DMA transfer.
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21.2.4
Using H8S/2357 I/O Ports In the interface circuit of Figure 32 pin P1.1 of the H8S/2357 is configured as a general purpose output port. This pin drives the ISP1181B's WAKEUP input to generate a remote wake-up. The H8S/2357 has 3 registers to configure port 1: Port 1 Data Direction Register (P1DDR), Port 1 Data Register (P1DR) and Port 1 Register (PORT1). Only registers P1DDR and P1DR must be configured, register PORT1 is only used to read the actual levels on the port pins.
* H8S/2357:
- select pin P1.1 to be an output in register P1DDR - program the desired bit value for P1.1 in register P1DR.
22. Test information
The dynamic characteristics of the analog I/O ports (D+ and D-) as listed in Table 56, were determined using the circuit shown in Figure 34.
test point 22 D.U.T 15 k CL 50 pF
MGS784
Load capacitance: CL = 50 pF (full-speed mode) Speed: full-speed mode only: internal 1.5 k pull-up resistor on D+
Fig 34. Load impedance for D+ and D- pins.
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23. Package outline
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1
D
E
A X
c y HE vMA
Z
48
25
Q A2 A1 pin 1 index Lp L (A 3) A
1
e bp
24
wM
detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions). UNIT mm A max. 1.2 A1 0.15 0.05 A2 1.05 0.85 A3 0.25 bp 0.28 0.17 c 0.2 0.1 D (1) 12.6 12.4 E (2) 6.2 6.0 e 0.5 HE 8.3 7.9 L 1 Lp 0.8 0.4 Q 0.50 0.35 v 0.25 w 0.08 y 0.1 Z 0.8 0.4 8 0o
o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT362-1 REFERENCES IEC JEDEC MO-153 EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-02-10 99-12-27
Fig 35. TSSOP48 package outline.
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HVQFN48: plastic thermal enhanced very thin quad flat package; no leads; 48 terminals; body 7 x 7 x 0.85 mm
D D1 B A
SOT619-2
A E1 E
A4 A1 c
terminal 1 index area
detail X
e1 terminal 1 index area L 48 e 1
1/2
C e b 12 13 e vMCAB wMC y1 C y
Eh
1/2
e2 e
37 36 Dh 0 DIMENSIONS (mm are the original dimensions) A UNIT max. mm 1 A1 0.05 0.00 A4 0.80 0.65 b 0.30 0.18 c 0.2 D 7.15 6.85 D1 6.85 6.65 Dh 5.25 4.95 E 7.15 6.85 25
24
X 2.5 scale 5 mm
E1 6.85 6.65
Eh 5.25 4.95
e 0.5
e1 5.5
e2 5.5
L 0.5 0.3
v 0.1
w 0.05
y 0.05
y1 0.1
OUTLINE VERSION SOT619-2
REFERENCES IEC --JEDEC MO-220 JEITA ---
EUROPEAN PROJECTION
ISSUE DATE 01-03-01 02-05-17
Fig 36. HVQFN48 package outline.
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Product data
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65 of 70
Philips Semiconductors
ISP1181B
Full-speed USB interface
24. Soldering
24.1 Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended.
24.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 220 C for thick/large packages, and below 235 C small/thin packages.
24.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results:
* Use a double-wave soldering method comprising a turbulent wave with high
upward pressure followed by a smooth laminar wave.
* For packages with leads on two sides and a pitch (e):
- larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end.
* For packages with leads on four sides, the footprint must be placed at a 45 angle
to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners.
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Product data
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Philips Semiconductors
ISP1181B
Full-speed USB interface
During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.
24.4 Manual soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
24.5 Package related soldering information
Table 62: Package[1] BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC[4], SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO
[1] [2]
Suitability of surface mount IC packages for wave and reflow soldering methods Soldering method Wave not suitable not suitable[3] Reflow[2] suitable suitable suitable suitable suitable
suitable not not recommended[4][5] recommended[6]
[3]
[4] [5] [6]
For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your Philips Semiconductors sales office. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
9397 750 09566
(c) Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 -- 03 July 2002
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Philips Semiconductors
ISP1181B
Full-speed USB interface
25. Revision history
Table 63: Rev Date 01 Revision history CPCN Description Product data; initial version.
20020703 -
9397 750 09566
(c) Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 -- 03 July 2002
68 of 70
Philips Semiconductors
ISP1181B
Full-speed USB interface
26. Data sheet status
Data sheet status[1] Objective data Preliminary data Product status[2] Development Qualification Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A.
Product data
Production
[1] [2]
Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
27. Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
29. Trademarks
ACPI -- is an open industry specification for PC power management, co-developed by Intel Corp., Microsoft Corp. and Toshiba GoodLink -- is a trademark of Koninklijke Philips Electronics N.V. OnNow -- is a trademark of Microsoft Corp. SoftConnect -- is a trademark of Koninklijke Philips Electronics N.V. Zip -- is a registered trademark of Iomega Corp.
28. Disclaimers
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors
Contact information
For additional information, please visit http://www.semiconductors.philips.com. For sales office addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com.
9397 750 09566
Fax: +31 40 27 24825
(c) Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 -- 03 July 2002
69 of 70
Philips Semiconductors
ISP1181B
Full-speed USB interface
Contents
1 2 3 4 5 6 6.1 6.2 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 8 9 9.1 9.2 9.3 9.4 9.5 10 10.1 10.2 10.3 10.4 10.4.1 10.4.2 11 11.1 11.1.1 11.2 11.3 12 12.1 12.1.1 12.1.2 12.1.3 12.1.4 12.1.5 12.1.6 12.1.7 12.1.8 12.2 12.2.1 12.2.2 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information. . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . . . . . . 9 Analog transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Philips Serial Interface Engine (SIE) . . . . . . . . . . . . . 9 Memory Management Unit (MMU) and integrated RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 SoftConnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 GoodLink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Bit clock recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 PLL clock multiplier . . . . . . . . . . . . . . . . . . . . . . . . . 10 Parallel I/O (PIO) and Direct Memory Access (DMA) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Endpoint descriptions. . . . . . . . . . . . . . . . . . . . . . . . 11 Endpoint access. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Endpoint FIFO size . . . . . . . . . . . . . . . . . . . . . . . . . 12 Endpoint initialization . . . . . . . . . . . . . . . . . . . . . . . . 14 Endpoint I/O mode access . . . . . . . . . . . . . . . . . . . . 14 Special actions on control endpoints . . . . . . . . . . . . 14 DMA transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Selecting an endpoint for DMA transfer . . . . . . . . . . 15 8237 compatible mode. . . . . . . . . . . . . . . . . . . . . . . 16 DACK-only mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 End-Of-Transfer conditions. . . . . . . . . . . . . . . . . . . . 18 Bulk endpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Isochronous endpoints . . . . . . . . . . . . . . . . . . . . . . . 19 Suspend and resume . . . . . . . . . . . . . . . . . . . . . . . . 20 Suspend conditions . . . . . . . . . . . . . . . . . . . . . . . . . 20 Powered-off application . . . . . . . . . . . . . . . . . . . . . . 21 Resume conditions. . . . . . . . . . . . . . . . . . . . . . . . . . 22 Control bits in suspend and resume. . . . . . . . . . . . . 23 Commands and registers . . . . . . . . . . . . . . . . . . . . . 23 Initialization commands . . . . . . . . . . . . . . . . . . . . . . 25 Write/Read Endpoint Configuration . . . . . . . . . . . . . 26 Write/Read Device Address . . . . . . . . . . . . . . . . . . . 26 Write/Read Mode Register. . . . . . . . . . . . . . . . . . . . 27 Write/Read Hardware Configuration . . . . . . . . . . . . 28 Write/Read Interrupt Enable Register . . . . . . . . . . . 29 Write/Read DMA Configuration . . . . . . . . . . . . . . . . 30 Write/Read DMA Counter . . . . . . . . . . . . . . . . . . . . 31 Reset Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Data flow commands . . . . . . . . . . . . . . . . . . . . . . . . 32 Write/Read Endpoint Buffer . . . . . . . . . . . . . . . . . . . 32 Read Endpoint Status . . . . . . . . . . . . . . . . . . . . . . . 34 12.2.3 12.2.4 12.2.5 12.2.6 12.2.7 12.3 12.3.1 12.3.2 12.3.3 12.3.4 12.3.5 12.3.6 13 14 15 16 17 17.1 18 19 20 20.1 20.2 20.3 20.4 20.5 21 21.1 21.2 21.2.1 21.2.2 21.2.3 21.2.4 22 23 24 24.1 24.2 24.3 24.4 24.5 25 26 27 28 29 Stall Endpoint/Unstall Endpoint . . . . . . . . . . . . . . . . Validate Endpoint Buffer . . . . . . . . . . . . . . . . . . . . . . Clear Endpoint Buffer . . . . . . . . . . . . . . . . . . . . . . . . Check Endpoint Status . . . . . . . . . . . . . . . . . . . . . . . Acknowledge Setup . . . . . . . . . . . . . . . . . . . . . . . . . General commands . . . . . . . . . . . . . . . . . . . . . . . . . Read Endpoint Error Code . . . . . . . . . . . . . . . . . . . . Unlock Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write/Read Scratch Register . . . . . . . . . . . . . . . . . . Read Frame Number . . . . . . . . . . . . . . . . . . . . . . . . Read Chip ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read Interrupt Register . . . . . . . . . . . . . . . . . . . . . . Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Crystal oscillator and LazyClock . . . . . . . . . . . . . . . Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended operating condition . . . . . . . . . . . . . Static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . Dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing symbols. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel I/O timing . . . . . . . . . . . . . . . . . . . . . . . . . . . Access cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . DMA timing: single-cycle mode . . . . . . . . . . . . . . . . DMA timing: burst mode . . . . . . . . . . . . . . . . . . . . . . Application information . . . . . . . . . . . . . . . . . . . . . . . Typical interface circuits . . . . . . . . . . . . . . . . . . . . . . Interfacing ISP1181B with an H8S/2357 microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt handling . . . . . . . . . . . . . . . . . . . . . . . . . . . Address mapping in H8S/2357 . . . . . . . . . . . . . . . . . Using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using H8S/2357 I/O Ports . . . . . . . . . . . . . . . . . . . . Test information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Soldering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction to soldering surface mount packages . . Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Manual soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . Package related soldering information . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . . . . . . . Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 35 35 35 36 36 36 37 38 38 39 40 41 43 43 45 46 46 47 49 51 51 52 54 55 58 60 60 62 62 62 62 63 63 64 66 66 66 66 67 67 68 69 69 69 69
(c) Koninklijke Philips Electronics N.V. 2002. Printed in The Netherlands
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 03 July 2002 Document order number: 9397 750 09566

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